公开(公告)号：US20080091907A1

公开(公告)日：2008-04-17

申请号：US11953803

申请日：2007-12-10

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarre ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarre ,  David Nguyen

IPC分类号： G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.

摘要翻译： 集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。 指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

公开(公告)号：US20070198868A1

公开(公告)日：2007-08-23

申请号：US11692162

申请日：2007-03-27

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： H04L7/033

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.

摘要翻译： 存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。 第二个互连传送写入命令和读取命令。 第三个互连传送写入数据和读取数据。 集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。 存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。 应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。 在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。

公开(公告)号：US20070147143A1

公开(公告)日：2007-06-28

申请号：US11681375

申请日：2007-03-02

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.

摘要翻译： 集成电路存储器件具有第一组引脚，以使用时钟信号接收行地址，后跟列地址。 器件具有第二组引脚，用于使用时钟信号接收检测命令和写入命令。 sense命令指定设备激活由行地址标识的一行存储器单元。 write命令指定存储器件接收写入数据，并将写入数据存储在由列地址标识的存储单元行中的位置。 在从第二组引脚接收写入命令的第一时间段开始第一个延迟之后，将写入命令内部发布到存储器件。 在从第一时间段开始第二延迟之后，在第三组引脚处接收写入数据。

公开(公告)号：US20050160241A1

公开(公告)日：2005-07-21

申请号：US11059216

申请日：2005-02-15

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C11/4096 ,  G06F12/16

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.

摘要翻译： 存储器件包括具有掩码引脚的互连和用于存储数据的存储器核。 存储器接口电路连接在互连和存储器核之间。 存储器接口电路选择性地处理来自掩码引脚的写掩码数据或来自掩码引脚的预充电指令信号。

公开(公告)号：US20070242532A1

公开(公告)日：2007-10-18

申请号：US11692159

申请日：2007-03-27

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G11C7/10 ,  G06F13/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.

摘要翻译： 集成电路存储器件包括第一组引脚和存储器核。 第一组引脚使用时钟信号接收写入命令和读取命令。 控制信息在接收到写入命令之后经过预定的延迟时间之后响应写入命令被发出，控制信息在存储器件中启动写入操作。 第二组引脚在从接收到读命令之后发生第一延迟时间后输出读数据。 第二组引脚的每个引脚在时钟信号的时钟周期期间输出两位读取数据。 第二组引脚还在接收到写入命令之后延迟了第二个延迟时间之后也接收到写入数据。 第二延迟时间基于第一延迟时间。

公开(公告)号：US20070159912A1

公开(公告)日：2007-07-12

申请号：US11681384

申请日：2007-03-02

申请人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

发明人： Richard Barth ,  Frederick Ware ,  Donald Stark ,  Craig Hampel ,  Paul Davis ,  Abhijit Abhyankar ,  James Gasbarro ,  David Nguyen

IPC分类号： G06F13/28 ,  G11C8/00 ,  G11C7/00 ,  G06F12/00

CPC分类号： G11C7/22 ,  G11C7/1006 ,  G11C7/12 ,  G11C8/12 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C2207/2218

摘要： An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.

摘要翻译： 具有延迟写入命令处理的集成电路存储器件包括耦合到存储器核心的第一组引脚，第一组引脚以接收列地址的行地址。 耦合到存储器核心的第二组引脚用于接收感测命令，后接写入命令。 感测命令指定感测由行地址识别的一行存储器单元，并且写入命令指定存储器件接收写入数据并将写入数据存储在由列地址标识的列位置处。 在从第二组引脚接收到写命令之后第一个延迟发生之后，写入命令在内部发布到存储器件中。

公开(公告)号：US20060022724A1

公开(公告)日：2006-02-02

申请号：US11237276

申请日：2005-09-27

申请人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

发明人： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

IPC分类号： H03L7/00

CPC分类号： G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

摘要： A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

公开(公告)号：US20070204184A1

公开(公告)日：2007-08-30

申请号：US11744006

申请日：2007-05-03

申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：US20070088968A1

公开(公告)日：2007-04-19

申请号：US11560031

申请日：2006-11-15

申请人： Scott Best ,  Abhijit Abhyankar ,  Kun Chang ,  Frank Lambrecht

发明人： Scott Best ,  Abhijit Abhyankar ,  Kun Chang ,  Frank Lambrecht

IPC分类号： G06F1/12

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。

公开(公告)号：US20050210308A1

公开(公告)日：2005-09-22

申请号：US10802634

申请日：2004-03-17

申请人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

发明人： Scott Best ,  Abhijit Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC分类号： G06F1/04 ,  H04L7/00 ,  H04L7/10 ,  H04L25/14

CPC分类号： G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

摘要： A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function.

摘要翻译： 通信信道包括具有耦合到正常信号源的发射机的第一分量和具有耦合到正常信号目的地的接收机的第二分量。 通信链路耦合第一和第二组件。 校准逻辑提供了设置通信信道参数的操作值，例如通过在链路初始化时执行穷举校准序列。 包括监视功能的跟踪电路通过监视具有与通信信道中的漂移相关的特征的反馈信号来跟踪参数中的漂移，并且更新或指示更新参数的操作值的需要 响应监控功能。