公开(公告)号：US06252803B1

公开(公告)日：2001-06-26

申请号：US09692881

申请日：2000-10-23

申请人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

发明人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland ,  Chi Chang

IPC分类号： G11C1616

CPC分类号： G11C16/16

摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.

摘要翻译： 提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。 擦除脉冲被施加到多个存储单元。 多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。 重复此循环，直到所有的单元格都被验证为不被过高。 多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。 重复此循环，直到所有单元格都被验证为不被忽略。 在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。 重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。 当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

公开(公告)号：US06400608B1

公开(公告)日：2002-06-04

申请号：US09842288

申请日：2001-04-25

申请人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland

发明人： Richard Fastow ,  Sameer S. Haddad ,  Lee E. Cleveland

IPC分类号： G11C1134

CPC分类号： G11C16/3422 ,  G11C16/344 ,  G11C16/3445

摘要： A technique is provided for reducing column leakage in a flash EEPROM device during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.

摘要翻译： 提供了一种在擦除验证过程中减少闪存EEPROM器件中的列泄漏的技术，从而防止虚假验证。 该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元并联连接。 该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行，从而防止虚假验证来进行操作。 该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

公开(公告)号：US06961267B1

公开(公告)日：2005-11-01

申请号：US10738301

申请日：2003-12-16

申请人： Richard M. Fastow ,  Lee E. Cleveland ,  Chi Chang

发明人： Richard M. Fastow ,  Lee E. Cleveland ,  Chi Chang

IPC分类号： G11C16/04 ,  G11C16/34

CPC分类号： G11C16/3468

摘要： Accurately programming a memory cell. A voltage is applied to a drain of the memory cell to program the cell. After applying the voltage, the cell is verified as to whether it is programmed to a desired level. The magnitude of the programming voltage is increased and applied to the drain, and the memory cell is re-verified for the desired level. This is repeated until the memory cell is programmed to the desired level. Additional memory cells are programmed in this fashion in order to program multiple memory cells in a narrow distribution around the desired level. The programming can be done one memory cell at a time or many cells can be programmed in parallel. Further a ramped programming voltage can applied to the gate of the memory cell(s), such that the ramped voltage to the gate and the ramped voltage to the drain both program the memory cell.

摘要翻译： 准确编程存储单元。 将电压施加到存储器单元的漏极以对单元进行编程。 在施加电压之后，验证单元是否被编程到所需的电平。 编程电压的大小被增加并施加到漏极，并且存储器单元被重新验证所需的电平。 直到将存储单元编程到所需的电平为止。 以这种方式对附加存储器单元进行编程，以便以围绕期望水平的窄分布来编程多个存储器单元。 编程可以一次完成一个存储单元，或者可以并行编程多个单元。 此外，斜坡编程电压可以施加到存储器单元的栅极，使得到栅极的斜坡电压和到漏极的斜坡电压都对存储器单元进行编程。

公开(公告)号：US5852582A

公开(公告)日：1998-12-22

申请号：US801305

申请日：1997-02-18

申请人： Lee E. Cleveland ,  Yuan Tang ,  Jonathan Su ,  Chi Chang ,  Chung K. Chang

发明人： Lee E. Cleveland ,  Yuan Tang ,  Jonathan Su ,  Chi Chang ,  Chung K. Chang

IPC分类号： G11C16/28 ,  G11C16/32 ,  G11C16/34 ,  G11C13/00

CPC分类号： G11C16/3431 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418

摘要： A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.

摘要翻译： 用于监视非易失性存储装置中的存储器阵列何时需要刷新的定时装置包括可编程半导体器件和检测装置，用于检测可编程半导体器件上的电荷量何时已降至至多阈值量。 在一个实施例中，可编程半导体器件是通过向浮动栅极增加电荷而编程的浮栅晶体管。 检测装置监视晶体管的IDS电流，并且当检测到多于可忽略的IDS电流量时，确定阵列刷新时间。

公开(公告)号：US06292425B1

公开(公告)日：2001-09-18

申请号：US09696652

申请日：2000-10-25

申请人： Ali K. Al-Shamma ,  Lee E. Cleveland

发明人： Ali K. Al-Shamma ,  Lee E. Cleveland

IPC分类号： G11C700

CPC分类号： G11C7/1006 ,  G11C7/1072

摘要： Power saving on the fly improves both the speed and power consumed in reading data from a core memory. Present data is selected from the core memory and clocked into the power saving arrangement. The present data is compared with previously selected data to determine whether the majority of data presently selected has changed from the previously selected data. In addition, the present selected data is also delayed and then subjected to a logical XOR function with the majority determination above. Finally, the data subjected to the logical XOR function and the majority determination are driven separately to external elements requesting the present data. Power is saved as the state of the majority of the data being driven from one data set to the next remains unchanged. Speed is increased as the data, once clocked into the arrangement, is driven in less than a clock pulse.

摘要翻译： 省电省电可以提高从内核读取数据所需的速度和功耗。 现有数据从核心存储器中选择并计入省电布置。 将当前数据与先前选择的数据进行比较，以确定当前选择的大部分数据是否已从先前选择的数据改变。 此外，当前选择的数据也被延迟，然后经过上述多数确定的逻辑XOR功能。 最后，经过逻辑异或功能和多数确定的数据分别驱动到请求本数据的外部元件。 由于从一个数据集驱动的大部分数据到下一个数据集的状态保持不变，所以功率被保存。 速度增加，因为数据一旦进入该装置，就以不到一个时钟脉冲驱动。

公开(公告)号：US5793249A

公开(公告)日：1998-08-11

申请号：US723558

申请日：1996-09-30

申请人： Jian Chen ,  Lee E. Cleveland

发明人： Jian Chen ,  Lee E. Cleveland

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C29/00 ,  G11C29/50 ,  H03M3/02 ,  H03K3/26 ,  H03G3/12

CPC分类号： G11C16/30 ,  G11C29/006 ,  G11C29/028 ,  G11C29/50 ,  G11C5/147 ,  G11C16/04 ,  G11C2029/5004

摘要： The system and method of enhancing the yield of flash memory circuit is disclosed. The method comprises performing a diagonal erase of a select group of memory cells on a wafer during sort. If the memory cells do not erase in a satisfactory manner, the control voltage applied to the memory cell is adjusted based on the memory cell's erase time. The circuitry for providing the adjustment voltage includes trimming circuitry for an incrementally increasing the applicable control of voltage.

摘要翻译： 公开了提高闪存电路的产量的系统和方法。 该方法包括在分类期间在晶片上执行选择存储单元组的对角线擦除。 如果存储器单元不以令人满意的方式擦除，则基于存储单元的擦除时间来调整施加到存储单元的控制电压。 用于提供调整电压的电路包括用于递增地增加电压的适用控制的微调电路。

公开(公告)号：US5579261A

公开(公告)日：1996-11-26

申请号：US426716

申请日：1995-04-21

申请人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

发明人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/02

CPC分类号： G11C16/3409 ,  G11C16/26 ,  G11C16/3404

摘要： A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.

摘要翻译： 一种用于使用热电子注入来连接到位线的闪存单元的阵列中的单元的编程方法。 在该方法中，将负字线电压施加到连接到位线的未选择的单元，以在未选择的单元中产生负栅极至源极电压。 提供未选择的单元中的负栅极到源极电压以防止过电压的单元或具有负阈值的单元导通以减少位线泄漏电流。

公开(公告)号：US5521867A

公开(公告)日：1996-05-28

申请号：US160057

申请日：1993-12-01

申请人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

发明人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404

摘要： A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.

摘要翻译： 用于提供紧密擦除阈值电压分布的闪速EPROM电路。 该电路包括具有门，源和漏极的存储器单元的阵列。 位线耦合到存储器阵列中的一列单元的漏极。 多个字线各自耦合到存储器阵列中的一行单元格的栅极。 第一电压源耦合到位线以会聚被擦除的存储器单元的阈值电压。 第二电压源耦合到字线以控制擦除的存储器单元的阈值电压。

公开(公告)号：US5349558A

公开(公告)日：1994-09-20

申请号：US112033

申请日：1993-08-26

申请人： Lee E. Cleveland ,  Michael A. Van Buskirk ,  Johnny C. Chen ,  Chung K. Chang

发明人： Lee E. Cleveland ,  Michael A. Van Buskirk ,  Johnny C. Chen ,  Chung K. Chang

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C29/808

摘要： An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors. Addressable storage circuitry (314a,314b) is used for storing sector-based redundancy column addresses, each defining a column address containing the defective column of memory cells in the plurality of sectors in association with one of the different redundant column segments to be used in repairing the defective column.

摘要翻译： 提供了一种用于快闪EEPROM单元阵列的改进的冗余架构，其允许以扇区为基础以冗余列的存储器单元来修复阵列中的存储器单元的有缺陷的列。 冗余电路包括多个基于扇区的冗余块（2-8），每个冗余块具有延伸穿过多个扇区的多个存储单元冗余列。 扇区选择晶体管（Q1，Q2）被提供用于将冗余列分成不同的段，每个段驻留在多个扇区中的至少一个扇区中，并且用于隔离不同的段，以允许独立使用同一冗余列中的其他段 在修复多个扇区中相应的扇区中的有缺陷的列。 可寻址存储电路（314a，314b）用于存储基于扇区的冗余列地址，每个定义包含多个扇区中的存储单元的缺陷列的列地址，与不同冗余列段之一相关联地使用 修理有缺陷的列。

公开(公告)号：US5612921A

公开(公告)日：1997-03-18

申请号：US559705

申请日：1996-02-15

申请人： Chung K. Chang ,  Johnny C. Chen ,  Lee E. Cleveland

发明人： Chung K. Chang ,  Johnny C. Chen ,  Lee E. Cleveland

IPC分类号： G11C5/14 ,  G11C16/30 ,  H02M3/07 ,  G11C13/00

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075

摘要： A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

摘要翻译： 用于在闪速擦除期间通过闪存EEPROM存储器单元阵列中的字线产生相对高的负电压以控制所选择的存储器单元的栅极的低电源负电荷泵包括由多个电荷泵级形成的电荷泵装置（210） 201-206）和用于将时钟信号传送到多个电荷泵级的耦合电容器装置（C201-C212）。 多个电荷泵级中的每一个由N沟道本征通过晶体管（N1-N6），N沟道本征初始化晶体管（MD1-MD6）和N沟道本征预充电晶体管（MX3-MX7， MX1），其设置在单独的p阱中，以减少身体效应。 结果，负电荷泵可以使用+ 3伏或更低的电源电压工作。