公开(公告)号：US5521867A

公开(公告)日：1996-05-28

申请号：US160057

申请日：1993-12-01

申请人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

发明人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404

摘要： A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.

摘要翻译： 用于提供紧密擦除阈值电压分布的闪速EPROM电路。 该电路包括具有门，源和漏极的存储器单元的阵列。 位线耦合到存储器阵列中的一列单元的漏极。 多个字线各自耦合到存储器阵列中的一行单元格的栅极。 第一电压源耦合到位线以会聚被擦除的存储器单元的阈值电压。 第二电压源耦合到字线以控制擦除的存储器单元的阈值电压。

公开(公告)号：US5579261A

公开(公告)日：1996-11-26

申请号：US426716

申请日：1995-04-21

申请人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

发明人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

IPC分类号： G11C16/26 ,  G11C16/34 ,  G11C16/02

CPC分类号： G11C16/3409 ,  G11C16/26 ,  G11C16/3404

摘要： A method for programing a cell in an array of flash memory cells connected to a bit line using hot-electron injection. In the method, a negative word line voltage is applied to unselected cells connected to the bit line to create a negative gate to source voltage in the unselected cells. The negative gate to source voltage in the unselected cells is provided to prevent overerased cells, or cells which have a negative threshold, from turning on to reduce bit line leakage current.

摘要翻译： 一种用于使用热电子注入来连接到位线的闪存单元的阵列中的单元的编程方法。 在该方法中，将负字线电压施加到连接到位线的未选择的单元，以在未选择的单元中产生负栅极至源极电压。 提供未选择的单元中的负栅极到源极电压以防止过电压的单元或具有负阈值的单元导通以减少位线泄漏电流。

公开(公告)号：US5576991A

公开(公告)日：1996-11-19

申请号：US269540

申请日：1994-07-01

申请人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

发明人： Nader Radjy ,  Lee E. Cleveland ,  Jian Chen ,  Shane C. Hollmer

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/16 ,  G11C16/34 ,  G11C11/40

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404

摘要： A method of converging threshold voltages of memory cells in a flash EEPROM array after the memory cells have been erased, the method including applying a gate voltage having an initial negative value which is increased to a more positive value in steps during application of a drain disturb voltage. By applying a gate voltage with an initial negative value, leakage current during convergence is reduced enabling all cells on bit lines of the array to be converged in parallel.

摘要翻译： 一种在存储器单元被擦除之后在闪存EEPROM阵列中会聚存储器单元的阈值电压的方法，该方法包括在施加漏极干扰期间施加具有初始负值的栅极电压，其逐步增加到更多的正值 电压。 通过施加具有初始负值的栅极电压，减小了会聚期间的漏电流，使得阵列的位线上的所有单元能够并行收敛。

公开(公告)号：US5598369A

公开(公告)日：1997-01-28

申请号：US484252

申请日：1995-06-07

申请人： Jian Chen ,  Nader Radjy

发明人： Jian Chen ,  Nader Radjy

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115

CPC分类号： G11C16/14 ,  H01L27/115

摘要： A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.

摘要翻译： 通过向单元的源极区域施加相对高的正电压，并且使单元的漏极区域和衬底区域的电压浮动，从而将电池的接地电位施加到电池的控制栅极，擦除快闪EEPROM单元阵列。 通过浮置衬底，由于唯一的直流电流路径在控制栅极和源极区域之间，擦除期间的源电流大大降低。 由于源极电流很小，所以不需要双扩散结，使得电池可以占用给定设计规则的最小面积，并且简化了电池制造工艺。 此外，抑制了高能量孔的产生，并且可以获得改善的性能。 由于在擦除操作期间源极电流较小，源极区域的高正电压可以通过片上电荷泵从低至+3V的电源电压产生。这简化了许多闪存的存储器板的设计 EEPROM芯片将被放置。 此外，由于在擦除期间将相对较高的正电压施加到源极区域，所以存储单元的后擦除Vt分布被紧固。 最后，由于在擦除操作期间，捕获在浮置栅极中的电子通过源极区域和控制栅极之间的重叠区域而不是通过沟道，所以对通道中的缺陷的产量灵敏度没有任何问题。

公开(公告)号：US5561620A

公开(公告)日：1996-10-01

申请号：US508425

申请日：1995-07-31

申请人： Jian Chen ,  Nader Radjy

发明人： Jian Chen ,  Nader Radjy

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/14 ,  H01L27/115

摘要： A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue of yield sensitivity to defects in the channel, since during the erasure operation, electrons trapped in the floating gate pass through the overlap region between the source region and the control gate, instead of through the channel.

摘要翻译： 通过向单元的源极区域施加相对高的正电压，并且使单元的漏极区域和衬底区域的电压浮动，从而将电池的接地电位施加到电池的控制栅极，擦除快闪EEPROM单元阵列。 通过浮置衬底，由于唯一的直流电流路径在控制栅极和源极区域之间，擦除期间的源电流大大降低。 由于源极电流很小，所以不需要双扩散结，使得电池可以占用给定设计规则的最小面积，并且简化了电池制造工艺。 此外，抑制了高能量孔的产生，并且可以获得改善的性能。 由于在擦除操作期间源极电流较小，源极区域的高正电压可以通过片上电荷泵从低至+3V的电源电压产生。这简化了许多闪存的存储器板的设计 EEPROM芯片将被放置。 此外，由于在擦除期间将相对较高的正电压施加到源极区域，所以存储单元的后擦除Vt分布被紧固。 最后，由于在擦除操作期间，捕获在浮置栅极中的电子通过源极区域和控制栅极之间的重叠区域而不是通过沟道，所以对通道中的缺陷的产量灵敏度没有任何问题。

公开(公告)号：US5978272A

公开(公告)日：1999-11-02

申请号：US871589

申请日：1997-06-06

申请人： Hao Fang ,  Sameer Haddad ,  Nader Radjy

发明人： Hao Fang ,  Sameer Haddad ,  Nader Radjy

IPC分类号： G11C16/04 ,  H01L29/423 ,  H01L29/788 ,  G11C11/34

CPC分类号： G11C16/0416 ,  H01L29/42324 ,  H01L29/7886 ,  G11C2216/10

摘要： A nonvolatile memory structure is disclosed. The nonvolatile memory structure includes a substrate, a heavily doped drain junction disposed in the substrate, and a lightly doped source junction disposed in the substrate. The source junction is diffused more deeply than the drain junction. The nonvolatile memory structure also includes a gate structure. The gate structure has a floating gate capacitively coupled to the substrate and a control gate capacitively coupled to the floating gate. The heavily doped drain junction has a central portion proximate to the gate structure. The lightly doped source junction also has a central portion proximate to the gate structure. At least the central portion of the lightly doped source junction is more lightly doped than the central portion of the heavily doped drain junction.

摘要翻译： 公开了非易失性存储器结构。 非易失性存储器结构包括衬底，设置在衬底中的重掺杂漏极结，以及设置在衬底中的轻掺杂源极结。 源极结比漏极结扩散更深。 非易失性存储器结构还包括栅极结构。 栅极结构具有电容耦合到衬底的浮动栅极和与浮动栅极电容耦合的控制栅极。 重掺杂漏极结具有靠近栅极结构的中心部分。 轻掺杂源极结还具有靠近栅极结构的中心部分。 至少轻掺杂源结的中心部分比重掺杂漏极结的中心部分更轻掺杂。

公开(公告)号：US5973372A

公开(公告)日：1999-10-26

申请号：US986283

申请日：1997-12-06

申请人： Farrokh Omid-Zohoor ,  Nader Radjy

发明人： Farrokh Omid-Zohoor ,  Nader Radjy

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/331 ,  H01L21/336 ,  H01L29/861

CPC分类号： H01L29/66515 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66272 ,  H01L29/66575

摘要： A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction in a single crystal substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with all of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and more conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.

摘要翻译： 在单晶衬底中的浅结上形成金属硅化物的方法及其结构，而不会通过在该结上的衬底上形成金属层而不会侵入到浅结上，接着形成一层硅材料，该层反应 其中金属比单晶衬底中的硅更快。 钛是优选的金属，非晶硅是优选的硅层，并且具有与所有钛反应的厚度。 两层快速热退火以形成硅化钛。 进行第二快速热退火，其将硅化钛的大多数C49相转换成较小电阻和更导电的C54相，并且在硅衬底和硅化钛之间形成硅外延层。

公开(公告)号：US5912842A

公开(公告)日：1999-06-15

申请号：US947850

申请日：1997-10-09

申请人： Shang-De Ted Chang ,  Vikram Kowshik ,  Andy Teng Feng Yu ,  Nader Radjy

发明人： Shang-De Ted Chang ,  Vikram Kowshik ,  Andy Teng Feng Yu ,  Nader Radjy

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L29/7885

摘要： A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

摘要翻译： 公开了一种非易失性存储器阵列，其包括多个PMOS双晶体管（2T）存储单元。 每个2T单元包括PMOS浮栅晶体管和PMOS选择晶体管，并且连接在位线和公共源极线之间。 公共行中的每个2T单元的选择栅极和控制栅极分别连接到字线和控制栅极线。 使用FN隧穿和BTBT诱导的热电子注入的组合对阵列的2T电池进行编程，并使用FN隧道擦除。 在一些实施例中，阵列被划分为扇区，其中每个扇区由n-阱区域定义并且包括预定数量的2T个单元的行。 这里，扇区中的每个2T单元的源耦合到扇区的公共源线。 在其他实施例中，阵列的位线沿着扇区边界被分段。

公开(公告)号：US6011272A

公开(公告)日：2000-01-04

申请号：US986284

申请日：1997-12-06

申请人： Farrokh Omid-Zohoor ,  Nader Radjy

发明人： Farrokh Omid-Zohoor ,  Nader Radjy

IPC分类号： H01L21/285 ,  H01L21/329 ,  H01L21/822 ,  H01L27/06 ,  H01L27/08 ,  H01L29/861 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/0814 ,  H01L21/28518 ,  H01L21/822 ,  H01L29/6609 ,  H01L29/8611 ,  H01L27/0629

摘要： A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction of a diode in a single crystalline substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with most of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and a more stable and conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide. The method and resulting structure can be used with a conventional method of fabricating diodes with different or varying breakdown voltages and leakage currents.

摘要翻译： 一种由此形成的方法及其结构，在单晶衬底中的二极管的浅结处形成金属硅化物，而不会通过在该结上的衬底上形成金属层而不侵入浅结，接着形成一层硅 与单晶衬底中的硅比金属更快地反应的材料。 钛是优选的金属，非晶硅是优选的硅层，并且具有与大部分钛反应的厚度。 两层快速热退火以形成硅化钛。 进行第二快速热退火，其将硅化钛的大多数C49相转换成较小电阻和更稳定且更导电的C54相，并且在硅衬底和硅化钛之间形成硅外延层。 该方法和结果可用于制造具有不同或变化的击穿电压和漏电流的二极管的常规方法。

公开(公告)号：US5966329A

公开(公告)日：1999-10-12

申请号：US948147

申请日：1997-10-09

申请人： Ching-Hsiang Hsu ,  Shang-De Ted Chang ,  Nader Radjy

发明人： Ching-Hsiang Hsu ,  Shang-De Ted Chang ,  Nader Radjy

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A program voltage of a first level is applied to the control gate of a PMOS floating gate memory cell to realize an injection of hot electrons induced by band-to-band tunneling (BTBT) into the floating gate of the cell. As the threshold voltage of the cell increases due to the accumulation of charge on the floating gate, the injection of BTBT induced hot electrons subsides. The program voltage is reduced to a second level which induces the injection of channel hot electrons (CHE) into the floating gate, thereby boosting the rate of charge accumulation on the floating gate.

摘要翻译： 第一电平的编程电压被施加到PMOS浮栅存储器单元的控制栅极，以实现由频带隧穿（BTBT）引起的热电子注入到电池的浮动栅极中。 随着电池的阈值电压由于浮动栅极上的电荷的积累而增加，BTBT引起的热电子的注入减弱。 程序电压降低到第二电平，其引起通道热电子（CHE）注入到浮置栅极中，从而提高浮置栅极上的电荷积累速率。