公开(公告)号：US20060281256A1

公开(公告)日：2006-12-14

申请号：US11312849

申请日：2005-12-20

申请人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

发明人： Richard Carter ,  Hemanshu Bhatt ,  Shiqun Gu ,  Peter Burke ,  James Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

IPC分类号： H01L21/336

CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

公开(公告)号：US07915122B2

公开(公告)日：2011-03-29

申请号：US11312849

申请日：2005-12-20

申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

IPC分类号： H01L21/336

CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

公开(公告)号：US20060292716A1

公开(公告)日：2006-12-28

申请号：US11329849

申请日：2006-01-11

申请人： Shiqun Gu ,  James Elmer ,  Peter Burke

发明人： Shiqun Gu ,  James Elmer ,  Peter Burke

IPC分类号： H01L21/00

CPC分类号： G11C13/02 ,  H01J1/304 ,  H01J9/025 ,  H01J2201/30469 ,  H01J2329/0455 ,  H01L21/76838 ,  H01L21/76879 ,  H01L2221/1094

摘要： Disclosed is a method of making a CNT device such as a memory switch, a field emission display, interconnect wiring, etc. The method includes steps of providing CNTs in contact with an electrode and selectively growing or depositing a layer of metal on top of the CNTs and the electrode. The layer of metal improves the electrical contact between the CNTs and the electrode. If a CNT memory switch is provided, the electrode can be embedded into dielectric or may lie on top of a dielectric substrate. In the case of interconnect wiring, an electrode can be provided embedded in dielectric and a via may be provided to the electrode. CNTs are disposed in the via, and the method provides that metal is selectively grown or deposited in the via, in contact with the CNTs and the electrode, thereby providing good electrical contact between the CNTs and the electrode.

摘要翻译： 公开了一种制造诸如存储器开关，场致发射显示器，互连布线等的CNT器件的方法。该方法包括以下步骤：提供与电极接触的CNT并选择性地生长或沉积金属层 碳纳米管和电极。 金属层改善了CNT和电极之间的电接触。 如果提供CNT存储器开关，则电极可以嵌入电介质中，或者可以位于电介质衬底的顶部。 在互连布线的情况下，可以将电极设置在电介质中，并且可以向电极提供通孔。 CNT布置在通孔中，并且该方法提供金属选择性地生长或沉积在与CNT和电极接触的通孔中，从而在CNT和电极之间提供良好的电接触。

公开(公告)号：US20070004191A1

公开(公告)日：2007-01-04

申请号：US11298274

申请日：2005-12-08

申请人： Shiqun Gu ,  Peter McGrath ,  James Elmer ,  Richard Carter

发明人： Shiqun Gu ,  Peter McGrath ,  James Elmer ,  Richard Carter

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  B82Y10/00 ,  H01L21/32136 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/742

摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后， 剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。

公开(公告)号：US20050064716A1

公开(公告)日：2005-03-24

申请号：US10951646

申请日：2004-09-28

申请人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

发明人： Hong Lin ,  Shiqun Gu ,  Wai Lo ,  James Elmer

IPC分类号： H01L21/28 ,  H01L21/311 ,  H01L29/51 ,  H01L29/80 ,  H01L21/302 ,  H01L21/461 ,  H01L31/112

CPC分类号： H01L29/518 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/31111 ,  H01L29/51 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an in-situ plasma species that causes structural damage to the exposed portions of the high k layer. The structurally damaged exposed portions of the high k layer are wet etched to leave the high k gate insulation layer.

摘要翻译： 在基板上的集成电路中形成高k栅极绝缘层的方法。 将高k层沉积在衬底上，并用掩模图案以限定高k栅极绝缘层和高k层的暴露部分。 高k层的暴露部分经受原位等离子体物质，这导致对高k层的暴露部分的结构损伤。 高k层的结构损坏的暴露部分被湿蚀刻以留下高k栅极绝缘层。

公开(公告)号：US07911034B2

公开(公告)日：2011-03-22

申请号：US12471175

申请日：2009-05-22

申请人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

发明人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

IPC分类号： H01L29/12

CPC分类号： H01L21/76838 ,  B82Y10/00 ,  H01L21/32136 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/742

摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away.

摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上（而不是完全通过）硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。 然后，剥离抗蚀剂和BARC层（如果提供的话），并且通过蚀刻掉（优选使用C1，F等离子体）将硬掩模图案有效地转移到CNT上，硬掩模的已经被部分蚀刻的部分 远。

公开(公告)号：US07538040B2

公开(公告)日：2009-05-26

申请号：US11298274

申请日：2005-12-08

申请人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

发明人： Shiqun Gu ,  Peter G. McGrath ,  James Elmer ,  Richard J. Carter ,  Thomas Rueckes

IPC分类号： H01L21/461

CPC分类号： H01L21/76838 ,  B82Y10/00 ,  H01L21/32136 ,  H01L21/32139 ,  H01L51/0018 ,  H01L51/0048 ,  Y10S977/742

摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.

摘要翻译： 一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。 然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后， 剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。

公开(公告)号：US09368716B2

公开(公告)日：2016-06-14

申请号：US12363886

申请日：2009-02-02

申请人： Shiqun Gu ,  Seung H. Kang ,  Xiaochun Zhu

发明人： Shiqun Gu ,  Seung H. Kang ,  Xiaochun Zhu

IPC分类号： H01L27/22 ,  H01L43/12 ,  H01L29/82 ,  H01L27/24 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L27/228 ,  H01L27/24 ,  H01L29/82 ,  H01L43/08

摘要： A magnetic tunnel junction storage element for a spin transfer torque magnetoresistive random access memory (STT-MRAM) bit cell includes a bottom electrode layer, a pinned layer adjacent to the bottom electrode layer, a dielectric layer encapsulating a portion of the bottom electrode layer and the pinned layer, the dielectric layer including sidewalls that define a hole adjacent to a portion of the pinned layer, a tunneling barrier adjacent to the pinned layer, a free layer adjacent to the tunneling barrier, and a top electrode adjacent to the free layer, wherein a width of the bottom electrode layer and/or the pinned barrier in a first direction is greater than a width of a contact area between the pinned layer and the tunneling barrier in the first direction. Also a method of forming an STT-MRAM bit cell.

摘要翻译： 用于自旋传递转矩磁阻随机存取存储器（STT-MRAM）位单元的磁性隧道结存储元件包括底部电极层，与底部电极层相邻的被钉扎层，封装底部电极层的一部分的电介质层和 被钉扎层，介电层包括限定与被钉扎层的一部分相邻的孔的侧壁，与被钉扎层相邻的隧道势垒，邻近隧道势垒的自由层和与自由层相邻的顶部电极， 其中所述底电极层和/或所述被钉扎的屏障在第一方向上的宽度大于所述被钉扎层和所述隧道势垒之间在所述第一方向上的接触面积的宽度。 也是形成STT-MRAM位单元的方法。

公开(公告)号：US08502373B2

公开(公告)日：2013-08-06

申请号：US12115076

申请日：2008-05-05

申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew Nowak

发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew Nowak

IPC分类号： H01L23/34

CPC分类号： H01L25/0657 ,  H01L23/3677 ,  H01L23/3732 ,  H01L23/3735 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/01019

摘要： By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

摘要翻译： 通过在层叠的IC器件的层之间填充导热材料，在一个层内的一个或多个位置处产生的热可以横向移位。 热的横向位移可以沿着层的整个长度，并且热材料可以是电绝缘的。 通过硅通孔（TSV）可以在某些位置构建，以帮助散热的位置。

公开(公告)号：US20120061804A1

公开(公告)日：2012-03-15

申请号：US13298884

申请日：2011-11-17

申请人： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew Nowak

发明人： Kenneth Kaskoun ,  Shiqun Gu ,  Matthew Nowak

IPC分类号： H01L25/065 ,  H01L21/98

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/60 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01093 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry.

摘要翻译： 在堆叠的半导体管芯的有源层之间的垂直空间中制造静电放电（ESD）保护装置，从而利用否则将仅用于通信目的的空间。 通过硅通孔（TSV）的垂直表面积用于吸收由ESD事件引起的大电压。 在一个实施例中，在层叠器件的半导体管芯的有源层之间的垂直TSV中产生ESD二极管。 该ESD二极管可以由堆叠的两个半导体管芯上的电路共享，从而节省了ESD保护电路所需的空间和减小管芯面积。