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1.发明授权Amorphous silicon photodiode with sloped sidewalls and method of fabrication 失效具有倾斜侧壁的非晶硅光电二极管和制造方法
公开(公告)号：US5191394A
公开(公告)日：1993-03-02
申请号：US783747
申请日：1991-10-28
IPC分类号： H01L21/3213 , H01L31/0216 , H01L31/0352 , H01L31/105 , H01L31/20
CPC分类号： H01L31/202 , H01L21/32137 , H01L31/02161 , H01L31/035281 , H01L31/1055 , Y02E10/50
摘要： Solid state photodetectors having amorphous silicon photodiode bodies with sloped sidewalls allowing for deposition of high integrity conformal layers thereover are produced by etching the amorphous silicon in a mostly anisotropic etchant in a reactive ion etcher in which the pressure of the etchant is controlled. A photoresist mask having sloped sidewalls is formed over the amorphous silicon to be etched and the pressure of the etchant is selected to produce the desired slope of the sidewall in the photodetector body; at lower pressures a smaller slope is produced in the silicon and at higher pressures a steeper slope is produced in the silicon.
摘要翻译： 具有倾斜侧壁的具有倾斜侧壁的固态光电二极管主体通过在其中控制蚀刻剂压力的反应离子蚀刻器中的大多数各向异性蚀刻剂中蚀刻非晶硅而产生。 在被蚀刻的非晶硅上形成具有倾斜侧壁的光致抗蚀剂掩模，并且选择蚀刻剂的压力以在光电检测器主体中产生所需侧壁的期望斜率; 在较低的压力下，在硅中产生较小的斜率，而在较高的压力下，在硅中产生更陡的斜率。
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2.发明授权Amorphous silicon photodiode with sloped sidewalls and method of fabrication 失效具有倾斜侧壁的非晶硅光电二极管及其制造方法
公开(公告)号：US5370972A
公开(公告)日：1994-12-06
申请号：US949954
申请日：1992-09-24
IPC分类号： H01L21/3213 , H01L31/0216 , H01L31/0352 , H01L31/105 , H01L31/20 , G03C5/00
CPC分类号： H01L31/202 , H01L21/32137 , H01L31/02161 , H01L31/035281 , H01L31/1055 , Y02E10/50
摘要： Solid state photodetectors having amorphous silicon photodiode bodies with sloped sidewalls allowing for deposition of high integrity conformal layers thereover are produced by etching the amorphous silicon in a mostly anisotropic etchant in a reactive ion etcher in which the pressure of the etchant is controlled. A photoresist mask having sloped sidewalls is formed over the amorphous silicon to be etched and the pressure of the etchant is selected to produce the desired slope of the sidewall in the photodetector body; at lower pressures a smaller slope is produced in the silicon and at higher pressures a steeper slope is produced in the silicon.
摘要翻译： 具有倾斜侧壁的具有倾斜侧壁的固态光电二极管主体通过在其中控制蚀刻剂的压力的反应离子蚀刻器中的大多数各向异性蚀刻剂中蚀刻非晶硅而产生。 在被蚀刻的非晶硅上形成具有倾斜侧壁的光致抗蚀剂掩模，并且选择蚀刻剂的压力以在光电检测器主体中产生所需侧壁的期望斜率; 在较低的压力下，在硅中产生较小的斜率，而在较高的压力下，在硅中产生更陡的斜率。
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3.发明授权Radiation imager with single passivation dielectric for transistor and diode 失效具有用于晶体管和二极管的单个钝化电介质的辐射成像仪
公开(公告)号：US5399884A
公开(公告)日：1995-03-21
申请号：US149888
申请日：1993-11-10
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L27/146 , H01L27/15 , H01L29/786 , H01L31/10 , H01L27/14
CPC分类号： H01L27/14643 , H01L27/1214
摘要： A radiation imager includes a photosensor array having a plurality of individually addressable pixels, each pixel having a photosensor island and an associated thin film transistor (TFT) disposed to selectively electrically couple the photosensor island to a predetermined address line. In each pixel a single common passivation layer is disposed over the TFT and the photosensor island such that the passivation layer is adjacent to both the outer surfaces of the TFT and portions of the photosensor island. In a method of fabricating a photosensor array as described above, after depositon of a source-drain metal layer, the layer is left unpatterned until after the photosensor island has been formed. In the formation of the photosensor island the source-drain metal layer serves as an etch stop to protect the TFT. Following formation of the photosensor island, the source-drain metal layer is patterned to form source and drain electrodes and fabrication of the TFT is completed. The single common passivation layer is then deposited over both the TFT and the photosensor island.
摘要翻译： 辐射成像仪包括具有多个可独立寻址的像素的光电传感器阵列，每个像素具有光电传感器岛和相关联的薄膜晶体管（TFT），用于选择性地将光电传感器岛电耦合到预定的地址线。 在每个像素中，单个公共钝化层设置在TFT和光电传感器岛上，使得钝化层与TFT的外表面和光电传感器岛的两个部分相邻。 在如上所述的制造光电传感器阵列的方法中，在源极 - 漏极金属层沉积之后，该层被保持未图案化，直到形成光电传感器岛为止。 在光电传感器岛的形成中，源极 - 漏极金属层用作蚀刻停止以保护TFT。 在形成光电传感器岛之后，对源极 - 漏极金属层进行图案化以形成源极和漏极并完成TFT的制造。 然后将单个公共钝化层沉积在TFT和光电传感器岛上。
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4.发明授权Method of fabricating a thin film transistor using hydrogen plasma treatment of the intrinsic silicon/doped layer interface 失效使用本征硅/掺杂层界面的氢等离子体处理制造薄膜晶体管的方法
公开(公告)号：US5281546A
公开(公告)日：1994-01-25
申请号：US939749
申请日：1992-09-02
IPC分类号： H01L21/30 , H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66765 , H01L21/3003 , H01L29/78669 , Y10S438/909 , Y10S438/91
摘要： A method of fabricating a thin film transistor (TFT) including the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer over the gate conductor; depositing a layer of amorphous silicon over the gate dielectric layer; treating the exposed surface of the amorphous silicon with a hydrogen plasma; depositing a layer of n+ doped silicon over the treated amorphous silicon surface such that an interface is formed between the amorphous silicon and the n+ doped layer that has relatively low contact resistance; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The TFT material layers are preferably deposited by plasma enhanced chemical vapor deposition. The hydrogen plasma treatment is advantageously used both when vacuum is maintained during the various deposition steps, and when vacuum is broken, for the purposes of patterning the amorphous silicon layer or the like, such that the amorphous silicon layer is passivated with the hydrogen plasma treatment prior to the deposition of the n+ doped layer.
摘要翻译： 一种制造薄膜晶体管（TFT）的方法，包括在基板上形成栅极导体的步骤; 在所述栅极导体上沉积栅极电介质层; 在所述栅极电介质层上沉积非晶硅层; 用氢等离子体处理非晶硅的暴露表面; 在经处理的非晶硅表面上沉积n +掺杂的硅层，使得在具有相对低的接触电阻的非晶硅和n +掺杂层之间形成界面; 在n +掺杂层上沉积一层源极/漏极金属化层; 以及图案化源极/漏极金属化层和下层n +掺杂层的部分以形成源极和漏极。 优选通过等离子体增强化学气相沉积来沉积TFT材料层。 有利地，当在各种沉积步骤期间保持真空并且当真空破裂时，为了图案化非晶硅层等的目的，有利地使用氢等离子体处理，使得非晶硅层被氢等离子体处理钝化 在沉积n +掺杂层之前。
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公开(公告)号：US5517031A
公开(公告)日：1996-05-14
申请号：US264097
申请日：1994-06-21
IPC分类号： H01L27/146 , G01T1/24
CPC分类号： H01L27/14625 , H01L27/14609 , H01L27/14623
摘要： A solid state radiation imager includes a photosensor array having a plurality of pixels disposed on a substrate, each pixel having a respective photosensor coupled to a thin film transistor (TFT). The photosensor array further includes an opaque passivation layer that is disposed over non-photodiode areas of the photosensor array, including the TFT and address lines in the array. The opaque passivation layer has an absorbance that is greater than 1, and typically that is greater than 2. The opaque passivation layer further is typically made of a thermally stable polymer mixed with a light absorbing material such as an organic dye (e.g., Sudan Black B), carbon black, or graphite.
摘要翻译： 固态放射线成像器包括具有设置在基板上的多个像素的光电传感器阵列，每个像素具有耦合到薄膜晶体管（TFT）的各自的光电传感器。 光电传感器阵列还包括不透明钝化层，其设置在光电传感器阵列的非光电二极管区域上，包括阵列中的TFT和地址线。 不透明钝化层的吸光度大于1，通常大于2.不透明钝化层通常由与光吸收材料（例如有机染料（例如，苏丹黑））混合的热稳定聚合物制成 B），炭黑或石墨。
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6.发明授权Radiation imager with common passivation dielectric for gate electrode and photosensor 失效具有公共钝化电介质的辐射成像仪用于栅电极和光电传感器
公开(公告)号：US5435608A
公开(公告)日：1995-07-25
申请号：US261592
申请日：1994-06-17
IPC分类号： H01L27/146 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14643 , Y10S438/958
摘要： A solid state radiation imager pixel having a thin film transistor (TFT) coupled to a photodiode in which the photodiode and the TFT each comprise a common dielectric layer, that is, a single dielectric layer that extends across the pixel and that has a gate dielectric layer portion and a photodiode body passivation portion. The common dielectric layer comprises a monolithic dielectric material such as silicon nitride or silicon oxide. Further, the bottom electrode of the photosensor body and the gate electrode are each disposed on a common surface of the substrate and comprise the same conductive material, the conductive material having been deposited on the pixel in the same deposition process. The source and drain electrodes and the common contact electrode for the photodiode each comprises the same source/drain metal conductive material, the conductive material having been deposited on the pixel in the same deposition process.
摘要翻译： 具有耦合到光电二极管的薄膜晶体管（TFT）的固态辐射成像器像素，其中光电二极管和TFT各自包括公共介电层，即，跨越像素延伸并具有栅极电介质的单个电介质层 层部分和光电二极管主体钝化部分。 公共介电层包括诸如氮化硅或氧化硅的单片电介质材料。 此外，光电传感器主体的底部电极和栅极电极分别设置在基板的公共表面上并且包括相同的导电材料，导电材料已经在相同的沉积工艺中沉积在像素上。 用于光电二极管的源电极和漏电极和公共接触电极每个包括相同的源极/漏极金属导电材料，导电材料已经以相同的沉积工艺沉积在像素上。
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公开(公告)号：US5198694A
公开(公告)日：1993-03-30
申请号：US825218
申请日：1992-01-24
IPC分类号： H01L21/3213 , H01L21/336 , H01L29/45
CPC分类号： H01L29/66765 , H01L21/32139 , H01L29/458 , Y10S438/97
摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
摘要翻译： 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量 共形钝化层的沉积。
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8.发明授权Method of fabricating radiation imager with single passivation dielectric for transistor and diode 失效用于晶体管和二极管制造单个钝化电介质的辐射成像仪的方法
公开(公告)号：US5516712A
公开(公告)日：1996-05-14
申请号：US330955
申请日：1994-10-28
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L27/146 , H01L27/15 , H01L29/786 , H01L31/10
CPC分类号： H01L27/14643 , H01L27/1214
摘要： A radiation imager includes a photosensor array having a plurality of individually addressable pixels, each pixel having a photosensor island and an associated thin film transistor (TFT) disposed to selectively electrically couple the photosensor island to a predetermined address line. In each pixel a single common passivation layer is disposed over the TFT and the photosensor island such that the passivation layer is adjacent to both the outer surfaces of the TFT and portions of the photosensor island. In a method of fabricating a photosensor array as described above, after depositon of a source-drain metal layer, the layer is left unpatterned until after the photosensor island has been formed. In the formation of the photosensor island the source-drain metal layer serves as an etch stop to protect the TFT. Following formation of the photosensor island, the source-drain metal layer is patterned to form source and drain electrodes and fabrication of the TFT is completed. The single common passivation layer is then deposited over both the TFT and the photosensor island.
摘要翻译： 辐射成像仪包括具有多个可独立寻址的像素的光电传感器阵列，每个像素具有光电传感器岛和相关联的薄膜晶体管（TFT），用于选择性地将光电传感器岛电耦合到预定的地址线。 在每个像素中，单个公共钝化层设置在TFT和光电传感器岛上，使得钝化层与TFT的外表面和光电传感器岛的两个部分相邻。 在如上所述的制造光电传感器阵列的方法中，在源极 - 漏极金属层沉积之后，该层被保持未图案化，直到形成光电传感器岛为止。 在光电传感器岛的形成中，源极 - 漏极金属层用作蚀刻停止以保护TFT。 在形成光电传感器岛之后，对源极 - 漏极金属层进行图案化以形成源极和漏极并完成TFT的制造。 然后将单个公共钝化层沉积在TFT和光电传感器岛上。
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9.发明授权Method of fabricating a radiation imager with common passivation dielectric for gate electrode and photosensor 失效制造具有用于栅电极和光电传感器的普通钝化电介质的辐射成像仪的方法
公开(公告)号：US5480810A
公开(公告)日：1996-01-02
申请号：US384093
申请日：1995-02-06
IPC分类号： H01L27/146 , H01L21/84 , H01L21/31
CPC分类号： H01L27/14643 , Y10S438/958
摘要： A solid state radiation imager pixel having a thin film transistor (TFT) coupled to a photodiode in which the photodiode and the TFT each comprise a common dielectric layer, that is, a single dielectric layer that extends across the pixel and that has a gate dielectric layer portion and a photodiode body passivation portion. The common dielectric layer comprises a monolithic dielectric material such as silicon nitride or silicon oxide. Further, the bottom electrode of the photosensor body and the gate electrode are each disposed on a common surface of the substrate and comprise the same conductive material, the conductive material having been deposited on the pixel in the same deposition process. The source and drain electrodes and the common contact electrode for the photodiode each comprises the same source/drain metal conductive material, the conductive material having been deposited on the pixel in the same deposition process.A method of fabricating an imager array includes, for each pixel in the array, the steps of depositing a first conductive layer on a substrate, forming a gate electrode and a photosensor bottom electrode from the first conductive layer, forming a photosensor body disposed on at least a portion of the photosensor bottom electrode, depositing a common dielectric layer over the gate electrode and over the photosensor body and exposed portion of the photosensor bottom electrode, and completing fabrication of the pixel TFT and the photosensor such that the TFT is electrically coupled to the respective photosensor. The portion of the common dielectric layer disposed over the gate electrode comprises the gate dielectric layer and the portion disposed over the photosensor body comprises the photosensor passivation layer.
摘要翻译： 具有耦合到光电二极管的薄膜晶体管（TFT）的固态辐射成像器像素，其中光电二极管和TFT各自包括公共介电层，即，跨越像素延伸并具有栅极电介质的单个电介质层 层部分和光电二极管主体钝化部分。 公共介电层包括诸如氮化硅或氧化硅的单片电介质材料。 此外，光电传感器主体的底部电极和栅极电极分别设置在基板的公共表面上并且包括相同的导电材料，导电材料已经在相同的沉积工艺中沉积在像素上。 用于光电二极管的源电极和漏电极和公共接触电极每个包括相同的源极/漏极金属导电材料，导电材料已经以相同的沉积工艺沉积在像素上。 制造成像器阵列的方法包括阵列中的每个像素，在第一导电层上沉积第一导电层的步骤，从第一导电层形成栅电极和光电传感器底电极，形成设在其上的光传感器体 光电传感器底部电极的至少一部分，在栅电极上方以及光电传感器主体和光电传感器底部电极的暴露部分之上沉积公共电介质层，并完成像素TFT和光电传感器的制造，使得TFT电耦合到 相应的光电传感器。 设置在栅极电极上的公共电介质层的部分包括栅极电介质层，并且设置在光电传感器主体上的部分包括光电传感器钝化层。
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10.发明授权Method of making a thin film transistor structure with improved source/drain contacts 失效制造具有改善的源极/漏极触点的薄膜晶体管结构的方法
公开(公告)号：US5362660A
公开(公告)日：1994-11-08
申请号：US977967
申请日：1992-11-18
IPC分类号： H01L21/3213 , H01L21/336 , H01L29/45 , H01L21/265
CPC分类号： H01L29/66765 , H01L21/32139 , H01L29/458 , Y10S438/97
摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
摘要翻译： 通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。 第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。 该蚀刻优选使用干蚀刻进行。 干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。 第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量 共形钝化层的沉积。
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