公开(公告)号：US20050186747A1

公开(公告)日：2005-08-25

申请号：US10786901

申请日：2004-02-25

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/339 ,  H01L21/60 ,  H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20060189061A1

公开(公告)日：2006-08-24

申请号：US11407313

申请日：2006-04-19

申请人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

发明人： Ricky Amos ,  Diane Boyd ,  Cyril Cabral ,  Richard Kaplan ,  Jakub Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda Mocuta ,  Vijay Narayanan ,  An Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US07056782B2

公开(公告)日：2006-06-06

申请号：US10786901

申请日：2004-02-25

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

公开(公告)号：US20050051854A1

公开(公告)日：2005-03-10

申请号：US10605106

申请日：2003-09-09

申请人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

发明人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

摘要翻译： 提供了一种用于高性能器件的金属替换栅极的结构和方法。 首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。 在牺牲栅极结构的侧壁上设置一对间隔物。 然后去除牺牲栅极结构，形成开口。 随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

公开(公告)号：US07655557B2

公开(公告)日：2010-02-02

申请号：US12145113

申请日：2008-06-24

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US20080254622A1

公开(公告)日：2008-10-16

申请号：US12145113

申请日：2008-06-24

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US07411227B2

公开(公告)日：2008-08-12

申请号：US11407313

申请日：2006-04-19

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaren Surendra

IPC分类号： H01L27/10 ,  H01L29/73

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

摘要翻译： 本发明提供了一种互补金属氧化物半导体集成工艺，其中在栅极电介质顶部制造多个硅化金属栅极。 使用本发明的集成方案形成的每个硅化金属栅极与硅化物金属栅极的尺寸无关，具有相同的硅化物金属相和基本上相同的高度。 本发明还提供了形成具有硅化物触点的CMOS结构的各种方法，其中多晶硅栅极高度在半导体结构的整个表面上基本相同。

公开(公告)号：US06921711B2

公开(公告)日：2005-07-26

申请号：US10605106

申请日：2003-09-09

申请人： Cyril Cabral, Jr. ,  Paul C. Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An L Steegen ,  Yun-Yu Wang ,  Kwong H. Wong

发明人： Cyril Cabral, Jr. ,  Paul C. Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An L Steegen ,  Yun-Yu Wang ,  Kwong H. Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/443

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

摘要翻译： 提供了一种用于高性能器件的金属替换栅极的结构和方法。 首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。 在牺牲栅极结构的侧壁上设置一对间隔物。 然后去除牺牲栅极结构，形成开口。 随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

公开(公告)号：US20220003626A1

公开(公告)日：2022-01-06

申请号：US16995955

申请日：2020-08-18

申请人： William Smith ,  Ying Li ,  Duncan Hywel-Evans

发明人： William Smith ,  Ying Li ,  Duncan Hywel-Evans

IPC分类号： G01M3/00

摘要： A leak detection system and method of use thereof is disclosed based on shock wave propagation in a fluid. In one form, the system includes at least one shock wave generator for introducing at least one shock wave signal into a fluid medium; at least one detector for detecting signals in the fluid medium; and at least one processor configured to identify excitation signals in the fluid medium caused by the at least one shock wave signal, wherein the identification of excitation signals is indicative of a fluid leak.

公开(公告)号：US09852430B2

公开(公告)日：2017-12-26

申请号：US11538309

申请日：2006-10-03

申请人： Ming Zhou ,  Cheng Niu ,  Zhaohui Tang ,  Ying Li ,  Chin-Yew Lin ,  Li Li ,  Brian Burdick

发明人： Ming Zhou ,  Cheng Niu ,  Zhaohui Tang ,  Ying Li ,  Chin-Yew Lin ,  Li Li ,  Brian Burdick

IPC分类号： G06Q30/00 ,  G06Q30/02

CPC分类号： G06Q30/02 ,  G06Q30/0242 ,  G06Q30/0255 ,  G06Q30/0261 ,  G06Q30/0269 ,  G06Q30/0276

摘要： Systems, methods, and computer-readable media for dynamically generating text associated with an advertisement are provided. Core text associated with an advertisement is received from an advertiser, as is at least one attribute relevant to the advertiser and/or a user. Based upon the received attribute(s), it is determined whether customization of the core text is desired. If customization is desired, the core text is modified and presented in association with the advertisement. If customization is not desired, the core text is presented in association with the advertisement. In one embodiment, target advertisement placement information may also be utilized to determine whether customization of the core text is desired.