公开(公告)号：US20050051854A1

公开(公告)日：2005-03-10

申请号：US10605106

申请日：2003-09-09

申请人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

发明人： Cyril Cabral ,  Paul Jamison ,  Victor Ku ,  Ying Li ,  Vijay Narayanan ,  An Steegen ,  Yun-Yu Wang ,  Kwong Wong

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/20 ,  H01L21/8234 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/66545 ,  H01L21/28079 ,  H01L29/4958

摘要： A structure and method for a metal replacement gate of a high performance device is provided. A sacrificial gate structure is first formed on an etch stop layer provided on a semiconductor substrate. A pair of spacers is provided on sidewalls of the sacrificial gate structure. The sacrificial gate structure is then removed, forming an opening. Subsequently, a metal gate including an first layer of metal such as tungsten, a diffusion barrier such as titanium nitride, and a second layer of metal such as tungsten is formed in the opening between the spacers.

摘要翻译： 提供了一种用于高性能器件的金属替换栅极的结构和方法。 首先在设置在半导体衬底上的蚀刻停止层上形成牺牲栅极结构。 在牺牲栅极结构的侧壁上设置一对间隔物。 然后去除牺牲栅极结构，形成开口。 随后，在间隔件之间的开口中形成包括诸如钨的第一金属层的金属栅，诸如氮化钛的扩散阻挡层和诸如钨的第二金属层。

公开(公告)号：US20060102968A1

公开(公告)日：2006-05-18

申请号：US10988733

申请日：2004-11-15

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L29/94

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor structure is provided that includes a Vt stabilization layer between a gate dielectric and a gate electrode. The Vt stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the proviso that when the Vt stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

摘要翻译： 提供了一种半导体结构，其包括在栅极电介质和栅电极之间的V 1稳定层。 VST稳定层能够将结构的阈值电压和平带电压稳定到目标值，并且包括氮化金属氧化物或无氮金属氧化物，条件是当V < 稳定层包括无氮金属氧化物，半导体衬底或栅极电介质中的至少一个包括氮。 本发明还提供一种制造这种结构的方法。

公开(公告)号：US20050250318A1

公开(公告)日：2005-11-10

申请号：US11180384

申请日：2005-07-13

申请人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijay Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/44 ,  H01L21/469 ,  H01L21/4763

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20060138603A1

公开(公告)日：2006-06-29

申请号：US11281032

申请日：2005-11-17

申请人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral ,  Alessandro Callegari ,  Michael Gribelyuk ,  Paul Jamison ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Deborah Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L23/58

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US20050104142A1

公开(公告)日：2005-05-19

申请号：US10712575

申请日：2003-11-13

申请人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

发明人： Vijav Narayanan ,  Fenton McFeely ,  Keith Milkove ,  John Yurkas ,  Matthew Copel ,  Paul Jamison ,  Roy Carruthers ,  Cyril Cabral ,  Edmund Sikorskii ,  Elizabeth Duch ,  Alessandro Callegari ,  Sufi Zafar ,  Kazuhito Nakamura

IPC分类号： C23C16/34 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78 ,  H01L29/76

CPC分类号： C23C16/34 ,  H01L21/28088 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/78

摘要： Compounds of Ta and N, potentially including further elements, and with a resistivity below about 20 mΩcm and with the elemental ratio of N to Ta greater than about 0.9 are disclosed for use as gate materials in field effect devices. A representative embodiment of such compounds, TaSiN, is stable at typical CMOS processing temperatures on SiO2 containing dielectric layers and high-k dielectric layers, with a workfunction close to that of n-type Si. Metallic Ta—N compounds are deposited by a chemical vapor deposition method using an alkylimidotris(dialkylamido)Ta species, such as tertiaryamylimidotris(dimethylamido)Ta (TAIMATA), as Ta precursor. The deposition is conformal allowing for flexible introduction of the Ta—N metallic compounds into a CMOS processing flow. Devices processed with TaN or TaSiN show near ideal characteristics.

摘要翻译： 公开了Ta和N的化合物，潜在地包括其它元素，并且电阻率低于约20mOmegacm，并且N与Ta的元素比大于约0.9，用作场效应器件中的栅极材料。 这种化合物的典型实施方案TaSiN在典型的CMOS处理温度下在含有介电层和高k电介质层的SiO 2 2上是稳定的，功函数接近n型Si的功函数。 金属Ta-N化合物通过化学气相沉积方法使用烷基亚氨基三（二烷基酰氨基）Ta种，例如叔戊酰亚胺基三（二甲基酰氨基）Ta（TAIMATA））作为Ta前体沉积。 沉积是共形的，允许将Ta-N金属化合物柔性引入CMOS加工流程。 用TaN或TaSiN处理的器件显示出接近理想的特性。

公开(公告)号：US20050280105A1

公开(公告)日：2005-12-22

申请号：US10873733

申请日：2004-06-22

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evengi Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上不会迁移率降低， 或更大。

公开(公告)号：US20060289903A1

公开(公告)日：2006-12-28

申请号：US11513101

申请日：2006-08-30

申请人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro Callegari ,  Eduard Cartier ,  Alessandro Curioni ,  Christopher D'Emic ,  Evgeni Gousev ,  Michael Gribelyuk ,  Paul Jamison ,  Rajarao Jammy ,  Dianne Lacey ,  Fenton McFeely ,  Vijay Narayanan ,  Carlo Pignedoli ,  Joseph Shepard ,  Sufi Zafar

IPC分类号： H01L31/112 ,  H01L29/80

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高移动性和低界面电荷的栅堆叠结构，以及包括其的半导体器件，即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 在本发明中使用的高温退火提供了一种栅堆叠结构，其具有通过电荷泵浦测量的约8×10 10电荷/ cm 2的界面态密度或 更少，约250cm 2 / Vs或更高的峰迁移率，并且在约6.0×10 12反转电荷/ cm 2处基本上没有迁移率降解， 或更大。

公开(公告)号：US20070090471A1

公开(公告)日：2007-04-26

申请号：US11259644

申请日：2005-10-26

申请人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

发明人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US20050156257A1

公开(公告)日：2005-07-21

申请号：US11066762

申请日：2005-02-28

申请人： Nestor Bojarczuk ,  Kevin Chan ,  Christopher D'Emic ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Lars-Ake Ragnarsson

发明人： Nestor Bojarczuk ,  Kevin Chan ,  Christopher D'Emic ,  Evgeni Gousev ,  Supratik Guha ,  Paul Jamison ,  Lars-Ake Ragnarsson

IPC分类号： H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28194

摘要： A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.

公开(公告)号：US20080099352A1

公开(公告)日：2008-05-01

申请号：US11752274

申请日：2007-05-22

申请人： Paul Jamison ,  Daniel Lee Bizzell

发明人： Paul Jamison ,  Daniel Lee Bizzell

IPC分类号： B65D25/08

CPC分类号： B65D23/003 ,  B65D1/04 ,  B65D1/095 ,  B65D25/22

摘要： A combination of a drinking container and a liquid dispenser comprises a drinking container defining an interior containment space for a beverage for human consumption and a liquid dispenser, which comprises a body defining an interior containment space and a structure by which the body of the liquid dispenser is mounted onto the drinking container such that the liquid dispenser does not obstruct drinking from a rim of the drinking container.

摘要翻译： 饮用容器和液体分配器的组合包括限定饮食用于人类消费的内部容纳空间的饮用容器和液体分配器，其包括限定内部容纳空间的主体和液体分配器的主体的结构 被安装到饮用容器上，使得液体分配器不阻碍从饮用容器的边缘饮用。