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112 条记录 (耗时 0.035 秒)

    Semiconductor device and method of fabricating the same
    1.
    发明申请
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US20050250317A1

    公开(公告)日：2005-11-10

    申请号：US11182150

    申请日：2005-07-15

    申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L21/44

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

    Semiconductor device and method of fabricating the same
    2.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US07611934B2

    公开(公告)日：2009-11-03

    申请号：US11182150

    申请日：2005-07-15

    申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

    Semiconductor device and method of fabricating the same
    3.
    发明授权
    Semiconductor device and method of fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06975001B2

    公开(公告)日：2005-12-13

    申请号：US10163984

    申请日：2002-06-06

    申请人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    发明人： Risho Koh ,  Yukishige Saito ,  Jong-Wook Lee ,  Hisashi Takemura

    IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

    CPC分类号： H01L27/1203 ,  H01L21/84

    摘要： A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

    摘要翻译： 半导体器件包括（a）形成在电绝缘层上的半导体层，（b）形成在半导体层上的栅极绝缘膜，（c）形成在栅极绝缘膜上的栅电极，以及（d）场绝缘 在半导体层上形成用于限定要制造半导体器件的区域的膜。 半导体层包括（a1）形成在栅极周围的半导体层中的源极和漏极区，源极和漏极区包含第一导电型杂质，（a2）形成在半导体层中的体接触区域， 包含第二导电型杂质，以及（a3）形成在半导体层中的载流子路径区域，使得载流子路径区域不与源区域和漏极区域接触，但与体接触区域接触，载体路径区域 含有第二导电型杂质。

    Vertical-type non-volatile memory devices and methods of manufacturing the same
    4.
    发明授权
    Vertical-type non-volatile memory devices and methods of manufacturing the same 有权
    垂直型非易失性存储器件及其制造方法

    公开(公告)号：US08236650B2

    公开(公告)日：2012-08-07

    申请号：US12686065

    申请日：2010-01-12

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

    Methods of manufacturing semiconductor devices including a doped silicon layer
    6.
    发明授权
    Methods of manufacturing semiconductor devices including a doped silicon layer 有权
    制造包括掺杂硅层的半导体器件的方法

    公开(公告)号：US08048784B2

    公开(公告)日：2011-11-01

    申请号：US12284565

    申请日：2008-09-23

    申请人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Pil-Kyu Kang ,  Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/36

    CPC分类号： H01L21/02532 ,  H01L21/02636 ,  H01L21/02675

    摘要： Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer.

    摘要翻译： 制造半导体器件的方法包括在衬底上形成含有硅材料的晶种层。 在种子层上形成含有非晶硅材料的非晶硅层。 非晶硅层掺杂有杂质。 将激光束照射到非晶硅层上以产生非晶硅层的相变，并且基于种子层将非晶硅层改变为单晶硅层。

    VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    7.
    发明申请
    VERTICAL-TYPE NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    垂直型非挥发性记忆体装置及其制造方法

    公开(公告)号：US20100112769A1

    公开(公告)日：2010-05-06

    申请号：US12686065

    申请日：2010-01-12

    申请人： Yong-Hoon Son ,  Jong-Wook Lee

    发明人： Yong-Hoon Son ,  Jong-Wook Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11556

    摘要： In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality to of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

    摘要翻译： 在半导体器件及其制造方法中，该器件包括在水平方向上延伸的单晶半导体材料的衬底和在衬底上的多个层间电介质层。 提供多个栅极图案，每个栅极图案位于相邻的下层间介电层和相邻的上层间电介质层之间。 单晶半导体材料的垂直沟道在垂直方向上延伸穿过多个层间电介质层和多个栅极图案，栅极绝缘层位于每个栅极图案和垂直沟道之间，其将栅极图案与垂直沟道绝缘 渠道。

    Vertical type semiconductor device
    8.
    发明申请
    Vertical type semiconductor device 有权
    垂直型半导体器件

    公开(公告)号：US20100109079A1

    公开(公告)日：2010-05-06

    申请号：US12588948

    申请日：2009-11-03

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7827 ,  H01L29/66666

    摘要： A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

    摘要翻译： 垂直柱半导体器件可以包括衬底，沟道图案组，栅极绝缘层图案和栅电极。 衬底可分为有源区和隔离层。 可以在对应于有源区的衬底中形成第一杂质区。 通道图案组可以从有源区域的表面突出并且可以彼此平行地布置。 第二杂质区可以形成在沟道图案组的上部。 栅极绝缘层图案可以形成在衬底和沟道图案组的侧壁上。 栅极绝缘层图案可以与沟道图案组的上表面间隔开。 栅电极可以接触栅极绝缘层并且可以包围沟道图案组的侧壁。

    Vertical semiconductor device, dram device including the same
    9.
    发明申请
    Vertical semiconductor device, dram device including the same 审中-公开
    垂直半导体器件，包括相同的电容器件

    公开(公告)号：US20100078698A1

    公开(公告)日：2010-04-01

    申请号：US12585776

    申请日：2009-09-24

    申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

    IPC分类号： H01L27/06 ,  H01L29/78

    CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

    摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

    摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。