公开(公告)号：US07964905B1

公开(公告)日：2011-06-21

申请号：US09591266

申请日：2000-06-09

申请人： Robert B. Ogle, Jr. ,  Marina V. Plat ,  Mark T. Ramsbey

发明人： Robert B. Ogle, Jr. ,  Marina V. Plat ,  Mark T. Ramsbey

IPC分类号： H01L29/94

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513

摘要： The invention provides core stacks for flash memory with an anti-reflective interpoly dielectric. Instead of requiring an anti-reflective coating at the top of the a stack, the present invention uses the interpoly layer as an anti-reflective coating in conjunction with a transmissive second polymer layer. Light is transmitted through the transmissive second polymer layer to the anti-reflective interpoly dielectric layer. The transmissive second polymer layer is formed from an amorphous silicon or polysilicon. Silicon oxynitride (SiON), as formed in the present invention, having a good dielectric constant K, is tailored in its index of refraction and in its thickness for utilization as both a good interpoly material and an anti-reflective coating.

摘要翻译： 本发明提供了具有抗反射互聚电介质的闪存的核心堆叠。 代替在堆叠的顶部需要抗反射涂层，本发明使用互聚层作为与透射性第二聚合物层结合的抗反射涂层。 光通过透射的第二聚合物层传输到抗反射的多聚电介质层。 透射的第二聚合物层由非晶硅或多晶硅形成。 在本发明中形成的具有良好的介电常数K的氮氧化硅（SiON）在其折射率和其厚度方面被适应为良好的间隙材料和抗反射涂层。

公开(公告)号：US06798002B1

公开(公告)日：2004-09-28

申请号：US09607675

申请日：2000-06-30

申请人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

发明人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

IPC分类号： H01L27108

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.

摘要翻译： 诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。 核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。 第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与 随后的植入和盐化步骤。

公开(公告)号：US06992370B1

公开(公告)日：2006-01-31

申请号：US10655179

申请日：2003-09-04

申请人： George J. Kluth ,  Robert B. Clark-Phelps ,  Joong S. Jeon ,  Huicai Zhong ,  Arvind Halliyal ,  Mark T. Ramsbey ,  Robert B. Ogle, Jr. ,  Kuo T. Chang ,  Wenmei Li

发明人： George J. Kluth ,  Robert B. Clark-Phelps ,  Joong S. Jeon ,  Huicai Zhong ,  Arvind Halliyal ,  Mark T. Ramsbey ,  Robert B. Ogle, Jr. ,  Kuo T. Chang ,  Wenmei Li

IPC分类号： H01L23/58 ,  H01L21/302

CPC分类号： H01L21/28282 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

摘要翻译： 根据一个实施例，存储单元结构包括半导体衬底，位于半导体衬底上的第一氧化硅层，位于第一氧化硅层之上的电荷存储层，位于电荷存储层上方的第二氧化硅层，以及 位于所述第二氧化硅层上方的栅极层。 在示例性实施例中，电荷存储层包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。 结果，降低的氢含量降低了电荷存储层中的电荷损失。 电荷存储层中的减少的电荷损失有利于减少存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

公开(公告)号：US06278166B1

公开(公告)日：2001-08-21

申请号：US08989741

申请日：1997-12-12

申请人： Robert B. Ogle, Jr.

发明人： Robert B. Ogle, Jr.

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/31662 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

摘要： The present invention provides a MOS structure and fabrication process for fabricating the substrate structure whereby a thin layer of silicon oxynitride, acting as a reaction barrier layer, and a tantalum pentoxide layer are formed in the gate region for controlling induction of electric charge in the gate region and thereby control the flow of current through the device. The high dielectric characteristic of the tantalum pentoxide facilitates blocking the flow of current in accordance with the applied voltage, and which in an off-state of the device, minimizes the gate leakage current. The silicon oxynitride barrier is formed by using a pre-deposition process of annealing the silicon substrate surface in a nitric oxide (NO) environment. The anneal may be a rapid thermal anneal (RTA) process for 10 seconds to 5 minutes at 400° C. to 1000° C. in the nitric oxide NO ambient. The annealing process produces the thin silicon oxynitride layer needed for depositing the tantalum pentoxide layer. After formation of the silicon oxynitride layer, the MOS structure undergoes a CVD deposition process for formation of a tantalum pentoxide layer on the silicon nitride surface. The silicon oxynitride layer formed using the pre-deposition anneal in nitric oxide (NO) (1) provides a hydrogen-free reaction barrier for depositing the tantalum pentoxide dielectric layer, (2) is formed at a lower temperature than a silicon nitride reaction barrier formed using ammonia, and (3) can function, when used alone, as a dielectric layer in applications that do not require the stringent off-state leakage current requirements. Other insulating material having a dielectric constant in the range of 25 to 80, such as titanium dioxide, may be formed over said silicon oxynitride layer for functioning as a reaction barrier layer.

摘要翻译： 本发明提供一种用于制造衬底结构的MOS结构和制造工艺，由此在用于控制栅极中的电荷感应的栅极区域中形成用作反应阻挡层的氧氮化硅薄层和五氧化二钽层 从而控制流过装置的电流。 五氧化二钽的高介电特性有助于根据所施加的电压阻断电流流动，并且在器件的断开状态下，使漏极电流最小化。 通过使用在一氧化氮（NO）环境中退火硅衬底表面的预沉积工艺来形成氧氮化硅屏障。 在一氧化氮NO环境中，退火可以是快速热退火（RTA）工艺在400℃至1000℃下10秒至5分钟。 退火过程产生沉积五氧化二钽层所需的薄氧氮化硅层。 在形成氮氧化硅层之后，MOS结构经历用于在氮化硅表面上形成五氧化二钽层的CVD沉积工艺。 在一氧化氮（NO）（1）中使用预沉积退火形成的氮氧化硅层提供了用于沉积五氧化二钽介电层的无氢反应势垒，（2）在比氮化硅反应阻挡层低的温度下形成 使用氨形成，并且（3）当不需要严格的截止状态漏电流要求的应用中，可以单独使用作为介电层。 介电常数在25〜80范围内的其他绝缘材料，例如二氧化钛，可以形成在所述氧氮化硅层上，用作反应阻挡层。

公开(公告)号：US06306777B1

公开(公告)日：2001-10-23

申请号：US09595166

申请日：2000-06-15

申请人： Robert B. Ogle, Jr. ,  Arvind Halliyal

发明人： Robert B. Ogle, Jr. ,  Arvind Halliyal

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L29/511

摘要： A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. Then at least three ambient reagent gases are selected from a group of reagent gases consisting essentially of N2O/NO, O2/H2O/O3, and NH3/N2. Any of the ambient reagent gases may be selected and utilized in a selected fabrication tools for pre-treating the surface of the bottom interpoly dielectric stack member prior to forming the complete interpoly dielectric stack of the flash memory element. The subsequently formed interpoly dielectric stack being a modified ONO stack where the post-treatment layer is disposed between the bottom silicon dioxide layer and the silicon nitride and silicon dioxide layers.

摘要翻译： 闪存结构和制造工艺，其中处理具有多层电介质堆叠的底层构件的第一多晶体或非晶硅材料（多晶硅）的堆叠，以在底部间隔层上形成后处理层 电介质层构件。 后处理层基本上是通过化学反应形成的固体材料，目的是改善多聚电介质堆叠的可靠性，并导致闪速存储元件的电容器耦合比的变化，并允许使用新的电源和编程 电压。 后处理层通过将具有底部间隔电介质层构件的多晶硅堆叠暴露于至少三种环境试剂气体中选定的一种来形成。 选择的环境试剂气体和半导体结构的暴露在分批炉，单晶片快速热退火工具或等离子体室中进行。 然后，从基本上由N 2 O / NO，O 2 / H 2 O / O 3和NH 3 / N 2组成的一组试剂气体中选择至少三种环境试剂气体。 可以在选择的制造工具中选择和使用任何环境试剂气体，以在形成闪速存储元件的完整的多余介电叠层之前预处理底部多聚电介质堆叠构件的表面。 随后形成的互间电介质叠层是修饰的ONO叠层，其中后处理层设置在底部二氧化硅层和氮化硅和二氧化硅层之间。

公开(公告)号：US07026211B1

公开(公告)日：2006-04-11

申请号：US10795890

申请日：2004-03-08

申请人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

发明人： Rinji Sugino ,  Joong S. Jeon ,  Robert B. Ogle, Jr.

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A semiconductor component having smooth, void-free conductive layers and a method for manufacturing the semiconductor component. Surface features such as gate structures are formed on a semiconductor substrate. A layer of insulating material is formed on the gate structures and a layer of polysilicon is formed on the layer of insulating material. The layer of polysilicon is annealed in a hydrogen ambient to redistribute the silicon atoms of the polysilicon layer. Redistribution of the atoms fills voids that may be present in the layer of polysilicon and smoothes the surface of the layer of polysilicon. Another layer of polysilicon is formed over the annealed layer of polysilicon. This polysilicon layer is annealed in a hydrogen ambient to redistribute the silicon atoms and smooth the surface of the polysilicon layer, thereby forming a subsequently annealed polysilicon layer. Control gate structures are formed from the subsequently annealed polysilicon layer.

摘要翻译： 具有光滑无空隙的导电层的半导体部件和半导体部件的制造方法。 诸如栅极结构的表面特征形成在半导体衬底上。 在栅极结构上形成绝缘材料层，在绝缘材料层上形成多晶硅层。 多晶硅层在氢环境中退火以重新分布多晶硅层的硅原子。 原子的再分布填充可能存在于多晶硅层中的空隙，并且平滑多晶硅层的表面。 在多晶硅的退火层上形成另一层多晶硅。 该多晶硅层在氢环境中退火以重新分配硅原子并平滑多晶硅层的表面，从而形成随后退火的多晶硅层。 控制栅结构由随后退火的多晶硅层形成。

公开(公告)号：US06716702B2

公开(公告)日：2004-04-06

申请号：US10291293

申请日：2002-11-08

申请人： Robert B. Ogle, Jr. ,  Arvind Halliyal

发明人： Robert B. Ogle, Jr. ,  Arvind Halliyal

IPC分类号： H01L21336

CPC分类号： H01L29/511 ,  H01L21/28273 ,  H01L29/42324

摘要： A flash memory structure and its fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material (polysilicon), are processed for formation of a pre-interpoly dielectric treatment layer over the first polysilicon material. The pre-interpoly dielectric treatment layer being a solid material formed by a chemical reaction formed for purposes of improving the reliability of an interpoly dielectric member and results in changing the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The pre-interpoly dielectric treatment layer is formed by exposing the polysilicon stacks to a selected one of at least three ambient reagent gases. The selected gaseous ambient and exposure of the polysilicon stacks being performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. The reagent gases consist essentially of: (1) nitrous oxide (N2O) and/or nitric oxide (NO), (2) oxygen (O2) and/or water (H2O), and (3) ammonia (NH3). Any one ambient reagent gas may be selected and utilized in any of the foregoing fabrication tools for pre-treating the surface of the first polysilicon stack prior to forming the interpoly dielectric structure member of the flash memory element. The interpoly dielectric member being a stack of silicon dioxide-silicon nitride-silicon dioxide material known as an ONO is thereon subsequently formed.

摘要翻译： 闪存结构及其制造工艺，其中第一多晶硅材料或非晶硅材料（多晶硅）的堆叠被处理以在第一多晶硅材料上形成预多晶硅介电处理层。 预互电介质处理层是通过化学反应形成的固体材料，为了提高多晶硅电介质的可靠性而导致改变闪存元件的电容器耦合比，并允许使用新的电源和 编程电压。 通过将多晶硅堆叠暴露于至少三种环境试剂气体中选定的一种来形成预多晶硅介电处理层。 所选择的气体环境和多晶硅堆叠的曝光在诸如间歇炉，单晶片快速热退火工具或等离子体室的制造工具中进行。 试剂气体基本上由以下组成：（1）一氧化二氮（N2O）和/或一氧化氮（NO），（2）氧（O 2）和/或水（H 2 O）和（3）氨（NH 3）。 任何一种环境反应气可以在任何前述的制造工具中被选择和使用，用于在形成闪速存储元件的多聚电介质结构构件之前预处理第一多晶硅叠层的表面。 作为被称为ONO的二氧化硅 - 氮化硅 - 二氧化硅材料的堆叠的多层电介质构件就在其上形成。

公开(公告)号：US06512264B1

公开(公告)日：2003-01-28

申请号：US09594207

申请日：2000-06-14

申请人： Robert B. Ogle, Jr. ,  Arvind Halliyal

发明人： Robert B. Ogle, Jr. ,  Arvind Halliyal

IPC分类号： H01L29788

CPC分类号： H01L29/511 ,  H01L21/28273 ,  H01L29/42324

摘要： A flash memory structure and its fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material (polysilicon), are processed for formation of a pre-interpoly dielectric treatment layer over the first polysilicon material. The pre-interpoly dielectric treatment layer being a solid material formed by a chemical reaction formed for purposes of improving the reliability of an interpoly dielectric member and results in changing the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The pre-interpoly dielectric treatment layer is formed by exposing the polysilicon stacks to a selected one of at least three ambient reagent gases. The selected gaseous ambient and exposure of the polysilicon stacks being performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. The reagent gases consist essentially of: (1) nitrous oxide (N2O) and/or nitric oxide (NO), (2) oxygen (O2) and/or water (H2O), and (3) ammonia (NH3). Any one ambient reagent gas may be selected and utilized in any of the foregoing fabrication tools for pre-treating the surface of the first polysilicon stack prior to forming the interpoly dielectric structure member of the flash memory element. The interpoly dielectric member being a stack of silicon dioxide-silicon nitride-silicon dioxide material known as an ONO is thereon subsequently formed.

摘要翻译： 闪存结构及其制造工艺，其中第一多晶硅材料或非晶硅材料（多晶硅）的堆叠被处理以在第一多晶硅材料上形成预多晶硅介电处理层。 预互电介质处理层是通过化学反应形成的固体材料，为了提高多晶硅电介质的可靠性而导致改变闪存元件的电容器耦合比，并允许使用新的电源和 编程电压。 通过将多晶硅堆叠暴露于至少三种环境试剂气体中选定的一种来形成预多晶硅介电处理层。 所选择的气体环境和多晶硅堆叠的曝光在诸如间歇炉，单晶片快速热退火工具或等离子体室的制造工具中进行。 试剂气体基本上由以下组成：（1）一氧化二氮（N2O）和/或一氧化氮（NO），（2）氧（O 2）和/或水（H 2 O）和（3）氨（NH 3）。 任何一种环境反应气可以在任何前述的制造工具中被选择和使用，用于在形成闪速存储元件的多聚电介质结构构件之前预处理第一多晶硅叠层的表面。 作为被称为ONO的二氧化硅 - 氮化硅 - 二氧化硅材料的堆叠的多层电介质构件就在其上形成。

公开(公告)号：US06355933B1

公开(公告)日：2002-03-12

申请号：US09229326

申请日：1999-01-13

申请人： Nicholas H. Tripsas ,  Robert B. Ogle, Jr.

发明人： Nicholas H. Tripsas ,  Robert B. Ogle, Jr.

IPC分类号： H01J3708

CPC分类号： H01J27/08 ,  H01J37/08 ,  H01J2237/022 ,  H01J2237/31701

摘要： Damaging forming deposits and etching is reduced in an ion source by introducing an oxygenated gas during operation of the ion source. Embodiments include an ion source in fluid communication with a source of oxygenated gas and introducing about 1% to about 10% of carbondioxide as the oxygenated gas together with a feed material.

摘要翻译： 通过在离子源的操作期间引入氧化气体，在离子源中减少形成沉积物和腐蚀。 实施例包括与氧化气体源流体连通的离子源，并将约1％至约10％的二氧化碳作为含氧气体与进料一起引入。