公开(公告)号：US06992370B1

公开(公告)日：2006-01-31

申请号：US10655179

申请日：2003-09-04

申请人： George J. Kluth ,  Robert B. Clark-Phelps ,  Joong S. Jeon ,  Huicai Zhong ,  Arvind Halliyal ,  Mark T. Ramsbey ,  Robert B. Ogle, Jr. ,  Kuo T. Chang ,  Wenmei Li

发明人： George J. Kluth ,  Robert B. Clark-Phelps ,  Joong S. Jeon ,  Huicai Zhong ,  Arvind Halliyal ,  Mark T. Ramsbey ,  Robert B. Ogle, Jr. ,  Kuo T. Chang ,  Wenmei Li

IPC分类号： H01L23/58 ,  H01L21/302

CPC分类号： H01L21/28282 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： According to one embodiment, a memory cell structure comprises a semiconductor substrate, a first silicon oxide layer situated over the semiconductor substrate, a charge storing layer situated over the first silicon oxide layer, a second silicon oxide layer situated over the charge storing layer, and a gate layer situated over the second silicon oxide layer. In the exemplary embodiment, the charge storing layer comprises silicon nitride having reduced hydrogen content, e.g., in the range of about 0 to 0.5 atomic percent. As a result, the reduced hydrogen content reduces the charge loss in the charge storing layer. The reduced charge loss in the charge storing layer has the benefit of reducing threshold voltage shifts, programming data loss, and programming capability loss in the memory device, thereby improving memory device performance.

摘要翻译： 根据一个实施例，存储单元结构包括半导体衬底，位于半导体衬底上的第一氧化硅层，位于第一氧化硅层之上的电荷存储层，位于电荷存储层上方的第二氧化硅层，以及 位于所述第二氧化硅层上方的栅极层。 在示例性实施例中，电荷存储层包括具有降低的氢含量的氮化硅，例如在约0至0.5原子百分比的范围内。 结果，降低的氢含量降低了电荷存储层中的电荷损失。 电荷存储层中的减少的电荷损失有利于减少存储器件中的阈值电压偏移，编程数据丢失和编程能力损失，从而提高存储器件性能。

公开(公告)号：US06798002B1

公开(公告)日：2004-09-28

申请号：US09607675

申请日：2000-06-30

申请人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

发明人： Robert B. Ogle, Jr. ,  Tuan D. Pham ,  Mark T. Ramsbey

IPC分类号： H01L27108

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： A dual gate semiconductor device, such as a flash memory semiconductor device, whose plurality of dual gate sidewall spacer structure is formed by a first and second anti-reflection fabrication process. The sidewall spacers of the dual transistor gate structures in the core memory region are left coated with the second anti-reflective coating material, after being used for gate patterning, to act as sidewall spacers for use in subsequent ion implant and salicidation fabrication steps. The second anti-reflective coating material is selected from a material group such as silicon oxynitride (SiON), silicon nitride (Si3N4), and silicon germanium (SiGe), or other anti-reflective coating material having optical properties and that are compatible with the subsequent implant and salicidation steps.

摘要翻译： 诸如闪存半导体器件的双栅极半导体器件，其多个双栅极侧壁间隔结构通过第一和第二抗反射制造工艺形成。 核心存储器区域中的双晶体管栅极结构的侧壁间隔物在用于栅极图案化之后被第二抗反射涂层材料涂覆以用作用于后续离子注入和盐化制造步骤的侧壁间隔物。 第二抗反射涂层材料选自诸如氮氧化硅（SiON），氮化硅（Si 3 N 4）和硅锗（SiGe）的材料组或具有光学性质的其它抗反射涂层材料，并且与 随后的植入和盐化步骤。

公开(公告)号：US07964905B1

公开(公告)日：2011-06-21

申请号：US09591266

申请日：2000-06-09

申请人： Robert B. Ogle, Jr. ,  Marina V. Plat ,  Mark T. Ramsbey

发明人： Robert B. Ogle, Jr. ,  Marina V. Plat ,  Mark T. Ramsbey

IPC分类号： H01L29/94

CPC分类号： H01L29/518 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/513

摘要： The invention provides core stacks for flash memory with an anti-reflective interpoly dielectric. Instead of requiring an anti-reflective coating at the top of the a stack, the present invention uses the interpoly layer as an anti-reflective coating in conjunction with a transmissive second polymer layer. Light is transmitted through the transmissive second polymer layer to the anti-reflective interpoly dielectric layer. The transmissive second polymer layer is formed from an amorphous silicon or polysilicon. Silicon oxynitride (SiON), as formed in the present invention, having a good dielectric constant K, is tailored in its index of refraction and in its thickness for utilization as both a good interpoly material and an anti-reflective coating.

摘要翻译： 本发明提供了具有抗反射互聚电介质的闪存的核心堆叠。 代替在堆叠的顶部需要抗反射涂层，本发明使用互聚层作为与透射性第二聚合物层结合的抗反射涂层。 光通过透射的第二聚合物层传输到抗反射的多聚电介质层。 透射的第二聚合物层由非晶硅或多晶硅形成。 在本发明中形成的具有良好的介电常数K的氮氧化硅（SiON）在其折射率和其厚度方面被适应为良好的间隙材料和抗反射涂层。

公开(公告)号：US06828199B2

公开(公告)日：2004-12-07

申请号：US10022798

申请日：2001-12-20

申请人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

发明人： Jusuke Ogura ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Zoran Krivokapic ,  Minh Van Ngo ,  Nicholas H. Tripisas

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/743 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.

摘要翻译： 用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。 通过ONO层和衬底产生凹陷。 在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。 在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。 硅化物例如由激光热退火形成。

公开(公告)号：US06548855B1

公开(公告)日：2003-04-15

申请号：US10147622

申请日：2002-05-16

申请人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

发明人： Mark T. Ramsbey ,  Arvind Halliyal ,  Kuo-Tung Chang ,  Nicholas H. Tripsas ,  Wei Zheng ,  Unsoon Kim

IPC分类号： H01L2976

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11539

摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.

摘要翻译： 一种用于在电力终止时保留数据的非易失性存储器件。 非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。 电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

公开(公告)号：US07670936B1

公开(公告)日：2010-03-02

申请号：US10273184

申请日：2002-10-18

申请人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

发明人： Arvind Halliyal ,  Nicholas H. Tripsas ,  Mark T. Ramsbey

IPC分类号： H01L21/425

CPC分类号： H01L21/268 ,  H01L21/02057 ,  H01L21/28202 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device includes forming an interface layer, a nitrided gate dielectric, a gate electrode, and source drain regions. The interface layer is formed in a substrate by laser processing. The nitrided gate dielectric is formed over the interface layer by laser processing. The gate electrode is formed over the substrate and the gate dielectric after the laser processing step, and source/drain regions are formed in the substrate proximate to the gate electrode.

摘要翻译： 制造半导体器件的方法包括形成界面层，氮化栅极电介质，栅电极和源漏区。 界面层通过激光加工形成在基板中。 通过激光加工在界面层上形成氮化栅极电介质。 在激光加工步骤之后，栅极电极形成在衬底和栅极电介质上，并且源极/漏极区域形成在靠近栅电极的衬底中。

公开(公告)号：US06774432B1

公开(公告)日：2004-08-10

申请号：US10358589

申请日：2003-02-05

申请人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

发明人： Minh V. Ngo ,  Tazrien Kamal ,  Mark T. Ramsbey ,  Arvind Halliyal ,  Jaeyong Park ,  Ning Cheng ,  Jeff P. Erhardt ,  Clarence B. Ferguson ,  Jeffrey A. Shields ,  Angela T. Hui ,  Robert A. Huertas ,  Tyagamohan Gottipati

IPC分类号： H01L29792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L23/552 ,  H01L27/115 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  Y10S438/954 ,  H01L2924/00

摘要： A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. A SONOS flash memory device, including a SONOS flash memory cell; and at least one UV-protective layer, in which the UV-protective layer comprises a substantially UV-opaque material, is provided. In one embodiment, the device includes a substantially UV-opaque contact cap layer.

摘要翻译： 一种保护SONOS闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造SONOS闪存单元; 并且在所述SONOS闪存单元上沉积至少一个UV保护层，所述UV保护层包括基本上不透紫外线的材料。 SONOS闪存设备，包括SONOS闪存单元; 以及至少一个UV保护层，其中UV保护层包括基本上不透紫外线的材料。 在一个实施例中，该装置包括基本上不透紫外线的接触盖层。

公开(公告)号：US06617215B1

公开(公告)日：2003-09-09

申请号：US10109235

申请日：2002-03-27

申请人： Arvind Halliyal ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Angela T. Hui ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Tazrien Kamal ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jean Y. Yang ,  Emmanuil Lingunis ,  Angela T. Hui ,  Jusuke Ogura

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L21/0332 ,  H01L21/32139 ,  H01L27/115

摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.

摘要翻译： 用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。 植入第一和第二位线，并存放字线材料。 硬掩模材料沉积在字线材料上。 硬掩模材料是具有沉积而不是生长的特征的材料。 光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。 去除图案化的光致抗蚀剂材料。 使用图案化的硬掩模处理字线材料以形成字线。 去除图案化的硬掩模材料。

公开(公告)号：US08368219B2

公开(公告)日：2013-02-05

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US08049334B1

公开(公告)日：2011-11-01

申请号：US12843131

申请日：2010-07-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffrey A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。