公开(公告)号：US5563833A

公开(公告)日：1996-10-08

申请号：US398465

申请日：1995-03-03

申请人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

发明人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

IPC分类号： G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/12 ,  G06F12/0893 ,  G11C15/00 ,  G11C8/10 ,  G11C29/10

摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。

公开(公告)号：US5841720A

公开(公告)日：1998-11-24

申请号：US918740

申请日：1997-08-26

申请人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

发明人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

IPC分类号： G11C11/413 ,  G11C7/14 ,  G11C8/18 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C7/02

CPC分类号： G11C8/18 ,  G11C7/14

摘要： A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.

摘要翻译： 一种存储器阵列，包括多个存储器单元，设定路径，信号路径以及用于将字线选择信号发送到存储器单元的行的至少一个字线。 字线从第一驱动器端延伸到第二端。 存储器阵列还包括从第一驱动器端延伸到第一端和第二端之间的点并返回到第一端的虚拟字线，用于响应于字线选择信号发送跟踪信号。 通过以这种方式折叠伪字线，实现了具有信号路径的设定路径的改进跟踪。

公开(公告)号：US06965503B2

公开(公告)日：2005-11-15

申请号：US10605441

申请日：2003-09-30

申请人： John Connor ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Alan L. Roberts

发明人： John Connor ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Alan L. Roberts

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0285

摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).

摘要翻译： 一种ESD保护电路，包括：一个或多个反相器（I 1，I 2，I 3），一个或多个反相器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT） 与一个或多个逆变器（I 1，I 2，I 3）中的至少一个的输出端连接的夹持装置（N 3）; 以及与RC网络（11）的钳位装置（N 3）和输出节点（RCT）通信的反馈装置（NKP）。 RC网络可以包括一个或多个电阻器和一个或多个去耦电容器。 在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I 1，I 2，I 3）中的每一个包括PFET和NFET对（P 0 / N 0，P 1 / N 1，P 2 / N 2）。

公开(公告)号：US5721957A

公开(公告)日：1998-02-24

申请号：US659045

申请日：1996-06-03

申请人： Lawrence P. Huang ,  David M. Svetlecic ,  Donald A. Evans ,  Alan L. Roberts

发明人： Lawrence P. Huang ,  David M. Svetlecic ,  Donald A. Evans ,  Alan L. Roberts

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3816 ,  G06F12/0886

摘要： A method and data processing system are disclosed for storing data in a cache memory and retrieving data from a cache memory in a selected one of multiple data formats. According to the present invention, bits are selected from an L-byte data word to produce N input words, which each have m bits. The N input words are then stored within the cache memory. In response to receipt of a request for data within the L-byte data word having a selected one of the multiple data formats, the N input words are recalled from the cache memory and simultaneously formatted to produce a P-byte formatted data word. Thus, a P-byte formatted data word is efficiently retrieved from the cache memory and formatted according to a selected one of multiple data formats before being utilized in the data processing system.

摘要翻译： 公开了一种方法和数据处理系统，用于将数据存储在高速缓冲存储器中，并以多种数据格式选择的一种从高速缓冲存储器检索数据。 根据本发明，从L字节数据字中选择位以产生N个输入字，每个输入字各具有m位。 然后将N个输入字存储在高速缓冲存储器中。 响应于在具有多个数据格式中选择的一个的L字节数据字中接收到对数据的请求，N个输入字从高速缓冲存储器中被调用并同时格式化以产生P字节格式的数据字。 因此，在数据处理系统中被利用之前，从高速缓冲存储器有效地检索P字节格式的数据字，并根据多种数据格式之一选择一种格式化。

公开(公告)号：US06396336B2

公开(公告)日：2002-05-28

申请号：US09883048

申请日：2001-06-15

申请人： Alan L. Roberts ,  Reid A. Wistort

发明人： Alan L. Roberts ,  Reid A. Wistort

IPC分类号： G05F110

CPC分类号： G11C5/147 ,  G11C11/417 ,  G11C2207/2227

摘要： The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage. The reference circuit reduces the reference voltage when the semiconductor enters the sleep mode from an activated mode and returns the reference voltage to the activated mode level when the semiconductor returns to the activated mode. The reducing step can be performed by reducing the current flow to one or more diodes in the reference circuit when the semiconductor enters the sleep mode from the activated mode, and increasing the current flow to the diodes when the semiconductor reenters the activated mode from the sleep mode.

摘要翻译： 当半导体处于睡眠模式时，半导体上的漏电流减小。 这通过（1）将半导体置于睡眠模式来实现; （2）向半导体提供从施加到半导体芯片的外部电源电压（其内部电源电压小于外部电源电压）得到的内部电源电压; 以及（3）当半导体返回到激活模式时，当半导体从激活模式进入睡眠模式时，降低内部电源电压并将内部电源电压恢复到激活模式电平。 所述还原步骤包括将外部电源电压提供给从其输出参考电压的参考电路; 并将参考电压提供给调节器，其中调节器尝试匹配参考电压并从其输出内部电源电压。 当半导体从激活模式进入睡眠模式时，参考电路降低参考电压，并且当半导体返回到激活模式时，将参考电压返回到激活模式电平。 当半导体从激活模式进入睡眠模式时，可以通过减少在参考电路中的一个或多个二极管的电流流动来进行还原步骤，并且当半导体从睡眠中重新启动激活模式时，增加到二极管的电流 模式。

公开(公告)号：US06333671B1

公开(公告)日：2001-12-25

申请号：US09433279

申请日：1999-11-03

申请人： Alan L. Roberts ,  Reid A. Wistort

发明人： Alan L. Roberts ,  Reid A. Wistort

IPC分类号： G05F110

CPC分类号： G11C5/147 ,  G11C11/417 ,  G11C2207/2227

摘要： The leakage current on a semiconductor is reduced while the semiconductor is in a sleep mode. This is accomplished by (1) placing the semiconductor in the sleep mode; (2) providing the semiconductor an internal supply voltage derived from an external supply voltage applied to the semiconductor chip (where the internal supply voltage is less in quantity than the external supply voltage); and (3) reducing the internal supply voltage when the semiconductor enters the sleep mode from an activated mode and returning the internal supply voltage to an activated mode level when the semiconductor returns to the activated mode. The reducing step includes supplying the external supply voltage to a reference circuit which outputs therefrom a reference voltage; and supplying the reference voltage to a regulator, where the regulator attempts to match the reference voltage and outputs therefrom the internal supply voltage. The reference circuit reduces the reference voltage when the semiconductor enters the sleep mode from an activated mode and returns the reference voltage to the activated mode level when the semiconductor returns to the activated mode. The reducing step can be performed by reducing the current flow to one or more diodes in the reference circuit when the semiconductor enters the sleep mode from the activated mode, and increasing the current flow to the diodes when the semiconductor reenters the activated mode from the sleep mode.

公开(公告)号：US5561781A

公开(公告)日：1996-10-01

申请号：US376275

申请日：1995-01-23

申请人： George M. Braceras ,  Alan L. Roberts

发明人： George M. Braceras ,  Alan L. Roberts

IPC分类号： G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0853

摘要： A virtual triple ported cache operates as a true triple ported array by using a pipelined array design. Multiple execution units can access the cache during the same cycle that the cache is updated from a main memory. The pipelined features of the cache allow for three separate sequential operations to occur within a single cycle, and thus give the appearance of a virtual triple ported array. This virtual triple port array architecture contains a data interface for dual execution units, which allows both units to access the same data array location. The array architecture allows for back-to-back read accesses occurring within a half cycle. The array architecture provides a bypassing function around the array for a write occurring on one port to the same address that a read is occurring on the other port. To allow for simultaneous cache reloads during execution unit access, a late write is done at the end of the cycle.

摘要翻译： 虚拟三端口缓存通过使用流水线阵列设计作为真正的三端口阵列来运行。 多个执行单元可以在从主存储器更新缓存的相同周期内访问高速缓存。 缓存的流水线功能允许在单个周期内进行三个单独的顺序操作，从而给出虚拟三端口阵列的外观。 该虚拟三端口阵列架构包含用于双执行单元的数据接口，允许两个单元访问相同的数据阵列位置。 阵列架构允许在半个周期内发生的背对背读取访问。 阵列架构在阵列周围提供绕过功能，用于将一个端口上的写入发生到另一个端口上发生读取的相同地址。 为了允许在执行单元访问期间同时进行高速缓存重新加载，在循环结束时完成一个迟写。

公开(公告)号：US06356981B1

公开(公告)日：2002-03-12

申请号：US09250772

申请日：1999-02-12

申请人： Alan L. Roberts ,  Reid A. Wistort

发明人： Alan L. Roberts ,  Reid A. Wistort

IPC分类号： G06F1200

CPC分类号： G11C7/1096 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/419 ,  G11C2207/2218 ,  G11C2207/2281 ,  G11C2207/229

摘要： An apparatus and method are provided that preserve data coherency within a DDR SRAM without sacrificing SRAM performance. The presence of a read-following-double-write (RFDW) condition is detected and data is prevented from being output from the SRAM following detection of the RFDW condition until coherent data is available. To detect an RFDW condition, preferably a double write signal is detected during a double write operation, and the double write signal is latched. A read signal also is detected during a read operation and the latched double write signal is compared to the read signal. If both the latched double write signal and the read signal are in a logic state that indicates that each is being performed, the RFDW condition is deemed detected. To prevent data from being pre-maturely output from the SRAM, the off chip driver circuitry of the SRAM preferably is maintained in a tri-state condition and data within a write buffer of the SRAM preferably is blocked until coherent data is available. A circuit for preserving data coherency in DDR SRAM circuitry is provided.

摘要翻译： 提供了在不牺牲SRAM性能的情况下保持DDR SRAM内的数据一致性的装置和方法。 检测到后跟双写（RFDW）条件的存在，并且在检测到RFDW条件之后，防止数据从SRAM输出，直到相干数据可用。 为了检测RFDW条件，优选在双重写入操作期间检测到双重写入信号，并且锁存双重写入信号。 在读操作期间也检测到读信号，并将锁存双写信号与读信号进行比较。 如果锁存的双重写入信号和读取信号都处于指示正在执行的逻辑状态，则认为检测到RFDW条件。 为了防止数据从SRAM中成熟地输出，SRAM的片外驱动器电路优选地保持在三态状态，并且优选地在SRAM的写入缓冲器内的数据被阻塞直到相干数据可用。 提供了一种用于在DDR SRAM电路中保持数据一致性的电路。

公开(公告)号：US06262911B1

公开(公告)日：2001-07-17

申请号：US09599774

申请日：2000-06-22

申请人： Geordie Braceras ,  William F. Pokorny ,  Alan L. Roberts

发明人： Geordie Braceras ,  William F. Pokorny ,  Alan L. Roberts

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： A method to statically balance Silicon-On-Insulator (SOI) parasitic effects is disclosed. Additionally, eight device Static Random Access Memory (SRAM) cells using the method are provided. A balanced output stage that creates a particular set of parasitic effects, as seen by a node connected to the output of the balanced output stage, is provided. If the balanced output stages are used at both outputs of a SRAM cell, the nodes to which the outputs of the balanced output stages are connected will see the same parasitic effects when the transistors in the balanced output stages are off. Thus, the balanced output stages can create the same effect on both the true and complement bitlines of an SOI SRAM, thereby balancing both of these lines and improving access times.

摘要翻译： 公开了一种用于静态平衡绝缘体上硅（SOI）寄生效应的方法。 另外，还提供了使用该方法的八个设备静态随机存取存储器（SRAM）单元。 提供了平衡输出级，其产生特定的一组寄生效应，如连接到平衡输出级的输出的节点所见。 如果在SRAM单元的两个输出端使用平衡输出级，则平衡输出级的输出端连接的节点在平衡输出级中的晶体管截止时将看到相同的寄生效应。 因此，平衡输出级可以对SOI SRAM的真实位线和补码位线产生相同的效果，从而平衡这两条线路并改善访问时间。