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1.发明授权Using one memory to supply addresses to an associated memory during testing 失效在测试期间使用一个内存来提供地址给相关的内存
公开(公告)号：US5563833A
公开(公告)日：1996-10-08
申请号：US398465
申请日：1995-03-03
申请人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
发明人： Robert D. Adams , John Connor , James J. Covino , Roy C. Flaker , Garrett S. Koch , Alan L. Roberts , Jose R. Sousa , Luigi Ternullo, Jr.
IPC分类号： G06F12/16 , G06F12/08 , G11C8/10 , G11C15/00 , G11C15/04 , G11C29/00 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/56 , G11C7/00
CPC分类号： G11C29/12 , G06F12/0893 , G11C15/00 , G11C8/10 , G11C29/10
摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.
摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。
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公开(公告)号：US5535164A
公开(公告)日：1996-07-09
申请号：US398468
申请日：1995-03-03
IPC分类号： G01R31/26 , G01R31/28 , G01R31/3185 , G06F7/02 , G11C29/00 , G11C29/12 , G11C29/26 , G11C29/40 , G11C29/56 , H01L21/66 , G11C7/00
CPC分类号： G11C29/26 , G01R31/318527 , G06F7/02 , G11C29/40
摘要： The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to "ignore" such signals, thereby generating the necessary signals to form the test patterns for each and every memory, the data and address information for those patterns, the control signals to write and read each memory, and capture error information for that particular memory. Hence, a single BIST can be used to test a multiplicity of memories of different sizes and different types.
摘要翻译： 本发明提供了一种可以通过使用状态机来选择和产生测试芯片上所有存储器所需的所有模式并且打印所有数据的不同尺寸，类型和特性的各种存储器，包括 预期数据和所有存储器的地址信息。 BIST还为各种存储器生成独特的（单独的）控制信号，并将这些控制信号印在各种存储器上。 BIST选择性地断言各种控制信号，以便仅对从其唯一控制被断言的那些存储器应用（写入）数据和仅读取和捕获（加载结果）故障信息。 存储器的写入使能信号的选择性断言防止对可能潜在地屏蔽单元写入和泄露缺陷的位置的多次写入，而只有在预期有效的存储器输出数据时执行存储器的负载结果信号的选择性断言，以便不捕获虚假错误信息 。 控制信号指示不使用特定输入序列或给定输入序列的任何部分的那些存储器“忽略”这样的信号，由此产生必要的信号以形成每个存储器的测试图案，数据和 这些模式的地址信息，用于写入和读取每个存储器的控制信号，以及捕获该特定存储器的错误信息。 因此，可以使用单个BIST来测试不同大小和不同类型的多个存储器。
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3.发明授权Memory array built-in self test circuit for testing multi-port memory arrays 失效内存阵列内置自检电路，用于测试多端口存储器阵列
公开(公告)号：US5796745A
公开(公告)日：1998-08-18
申请号：US684519
申请日：1996-07-19
CPC分类号： G11C29/20
摘要： A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-port memory array, a plurality of single-port memory arrays, or a combination thereof by providing unique read/write sequences to the same or to adjacent memory locations.
摘要翻译： 公开了一种内存自检（ABIST）电路，用于测试多端口存储器阵列。 用于ABIST电路的可编程模式发生器允许在多端口存储器阵列中的相同或相邻地址位置处执行不同的R / W数据操作。 可编程模式生成器包括数据发生器，读/写控制器和地址计数器，每个具有与多端口存储器阵列的端口相同数量的输出。 可编程模式发生器还包括频率控制器。 数据发生器用存储器阵列的适当数据模式进行编程，读/写控制器用适当的存储器阵列读/写模式进行编程。 地址计数器是在多端口阵列的每个端口上提供相同或不同的地址，并且频率控制器用适当的频率信息编程，以确定存储器阵列中每个单元的读/写操作的数量。 可编程数据，可编程读/写序列，可编程地址计数器和可编程频率的组合允许通过提供唯一的读/写来对多端口存储器阵列，多个单端口存储器阵列或其组合进行确定性测试 序列到相同或相邻的存储器位置。
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公开(公告)号：US4782250A
公开(公告)日：1988-11-01
申请号：US91565
申请日：1987-08-31
IPC分类号： H03K17/08 , H03K19/003 , H03K19/017 , H03K19/0185 , H03K19/094 , H03K19/0948 , H03K17/04 , H03K17/687 , H03K19/096
CPC分类号： H03K19/0948 , H03K19/00315 , H03K19/01721 , H03K19/09429
摘要： A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor arranged in series with a second or pull-up P-channel transistor and a third P-channel transistor connected from the common point between the first and second transistors and the gate electrode of the first transistor. The first and second transistors are disposed between a data output terminal and a first voltage source having a supply voltage of a given magnitude, with the data output terminal also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor, disposed in a common N-well with the other P-channel transistors, is connected at its source to the first voltage source and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.
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公开(公告)号：US5793592A
公开(公告)日：1998-08-11
申请号：US855187
申请日：1997-05-13
CPC分类号： H03K17/162
摘要： A topology for arranging a plurality of transistors between a signal source and an off-chip receiver, using a single power supply voltage. A pass through NFET has a gate controlled by a network comprised of two transistors arrayed between the power supply voltage and the drain of the NFET, which limits overshoots to the power supply voltage and reduces undershoots. Further reduction of undershoots is accomplished by an additional network of transistors, optimally including a PFET in series with the pass through NFET.
摘要翻译： 一种用于使用单个电源电压在信号源和片外接收器之间布置多个晶体管的拓扑。 通过NFET的通过栅极由网络控制，该网络由排列在电源电压和NFET的漏极之间的两个晶体管组成，其将过冲限制到电源电压并降低下冲。 通过附加的晶体管网络实现进一步减少下冲，最佳地包括与通过NFET串联的PFET。
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公开(公告)号：US07096810B1
公开(公告)日：2006-08-29
申请号：US11230383
申请日：2005-09-20
申请人： Robert D. Adams
发明人： Robert D. Adams
IPC分类号： B63B1/34
CPC分类号： B63B1/38 , B60F3/0007 , B63B2001/201 , B63H1/18 , B63H5/07 , B63H5/08 , B63H5/125 , B63H11/113 , B63H2005/005 , Y02T70/122
摘要： A bow mounted vessel propulsion system is designed to exploit the characteristics of a self-producing vessel lubricating boundary layer of air or air bubbles formed during water surface interaction by the vessel's hull during vessel movement. This boundary layer of air/air bubbles will be produced at the bow of the vessel and, during forward motion, is superimposed upon the surface of the water as the vessel's hull passes over, reducing the frictional drag of the hull as it moves across and through the water. The system has a propulsion means such as a water surface-piercing propeller or water jet nozzles, which will propel the vessel forward and, at the same time, by action of propeller rotation (drawing air into and intermixing) in the water or water jet movement, will create the air bubbles which produce the hull-lubricating phenomenon. The hull is a substantially flat-bottomed planning hull with two linear rails on each lengthwise outer edge of the bottom surface of the hull. The rails extend downward into the water at a sufficient depth to be able to keep the boundary layer of air bubbles from escaping out from the sides of the hull bottom when the vessel is in forward motion.
摘要翻译： 弓形船舶推进系统设计用于利用容器运动期间船舶船体在水面相互作用期间形成的空气或气泡的自生产容器润滑边界层的特性。 空气/气泡的这个边界层将在船只的弓处产生，并且在向前运动期间，随着船体的船体越过，它们叠加在水面上，从而减小了船体移动时的摩擦阻力， 通过水。 该系统具有诸如水面穿孔螺旋桨或水喷嘴的推进装置，其将推进船舶向前，并且同时通过螺旋桨旋转（将空气进入和混合）在水或水射流中的作用 运动，会产生产生船体润滑现象的气泡。 船体是一个基本上平底的规划船体，在船体底面的每个纵向外边缘上都有两根直线导轨。 轨道以足够的深度向下延伸到水中，以便当船舶向前运动时能够使气泡的边界层从船体底部的侧面逸出。
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公开(公告)号：USD347688S
公开(公告)日：1994-06-07
申请号：US898739
申请日：1992-06-15
申请人： Robert D. Adams
设计人： Robert D. Adams
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公开(公告)号：US5313424A
公开(公告)日：1994-05-17
申请号：US852587
申请日：1992-03-17
摘要： A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.
摘要翻译： 提供一种形成在半导体芯片上的冗余系统，其包括用于测试存储器阵列以定位故障元件的电路，用于存储故障元件的地址的寄存器和响应于存储在该存储器中的地址的二进制数字而被熔断的电熔丝 在从单个输入施加到半导体芯片的使能信号时，进行寄存。 使能信号通过芯片上的逻辑电路，使得熔丝不能被编程或熔断，除非使能信号存在。 耦合到保险丝的输出的地址解码器代替用于故障元件的冗余元件。
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公开(公告)号：USD458151S1
公开(公告)日：2002-06-04
申请号：US29133899
申请日：2000-12-08
申请人： Robert D. Adams
设计人： Robert D. Adams
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公开(公告)号：US6050977A
公开(公告)日：2000-04-18
申请号：US111325
申请日：1998-07-07
申请人： Robert D. Adams
发明人： Robert D. Adams
CPC分类号： A61M5/3234 , A61M2205/581
摘要： An improved syringe of the type having a hollow body which is closed at one end by an injection means and is open at the other end, the open end receives an elongated plunger means which moves through the hollow body and forces the contents of the body through the injection means. The improvement is comprised of an elastic member which retracts the injection means into a protective covering.
摘要翻译： 一种改进的注射器，其具有中空体，该中空体在一端通过注射装置封闭并且在另一端开口，开口端容纳细长的柱塞装置，其移动穿过中空体并迫使身体的内容物通过 注射装置。 该改进包括将注射装置缩回到保护罩中的弹性构件。
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