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公开(公告)号：US6130156A
公开(公告)日：2000-10-10
申请号：US281538
申请日：1999-03-30
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76843 , H01L21/76873 , H01L21/76876 , H01L21/76877 , H01L21/76886 , H01L2221/1089 , H01L23/53219 , H01L23/53233 , H01L2924/0002
摘要： A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.
摘要翻译： 一种制造互连的方法，其中最初提供第一层导电互连（3）。 形成通孔（7），其通过延伸到第一互连层的壁限定。 在导电互连和导电金属（11）的第一层之间形成一层钛（9）。 第一层导电金属形成在通孔的壁上，具有相对于特定蚀刻物质的预定蚀刻速率，并且第二层导电金属（13）形成在具有蚀刻的第一导电金属层上 相对于比第一层大的特定蚀刻物质的速率，并且优选地延伸到通孔中。 导电互连的第一层优选为铝，第一层导电金属优选为含有约1％至约100％铜的金属，其余基本上为铝，而第二层导电金属优选为 铜掺杂的铝的铜含量低于第一导电层。
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公开(公告)号：US06358849B1
公开(公告)日：2002-03-19
申请号：US09467680
申请日：1999-12-21
申请人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
发明人： Robert H. Havemann , Girish A. Dixit , Manoj Jain , Eden Zielinski , Qi-Zhong Hong , Jeffrey West
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31053 , H01L21/76224 , H01L21/76849 , H01L21/76856 , H01L21/76867
摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.
摘要翻译： 一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。 这在沟槽蚀刻期间通过底部保护提供。
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公开(公告)号：US06333265B1
公开(公告)日：2001-12-25
申请号：US08766199
申请日：1996-12-12
IPC分类号： H01L2144
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76843 , H01L21/76862
摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;
摘要翻译： 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地 在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。
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公开(公告)号：US06159847A
公开(公告)日：2000-12-12
申请号：US191027
申请日：1998-11-12
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L21/7685 , H01L21/76843 , H01L21/76877 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： AlCu alloys with higher Cu content are added in thin layers within a metallization structure. The increased Cu content provided by the thin layer improves interconnect reliability and reduces the effects of electromigration with minimal effect on plasma etch and cleanup processes.
摘要翻译： 具有较高Cu含量的AlCu合金以金属化结构内的薄层加入。 由薄层提供的增加的Cu含量提高了互连可靠性，并且减少电迁移的影响，对等离子体蚀刻和清除过程的影响最小。
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公开(公告)号：US06589865B2
公开(公告)日：2003-07-08
申请号：US09899194
申请日：2001-07-06
IPC分类号： H01L214763
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76843 , H01L21/76862
摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;
摘要翻译： 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有元素的无钛衬里以便于空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地不 大约30MPa，在约100°-300℃的温度范围内。以上述方式填充的凹坑表现出比通过常规实践填充的结构低30％的电阻水平。
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公开(公告)号：US06995439B1
公开(公告)日：2006-02-07
申请号：US10803234
申请日：2004-03-17
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/7682 , H01L2221/1047
摘要： Porous dielectric layers are produced by introducing small vertical or columnar gaps in pre-formed layers of dense dielectric. The pores may be formed by a special process that is different from the processes employed to form metal lines and other features on a VLSI device. Further, the columnar gaps may be produced after the planarization process for a particular layer has been completed. Then, after the pores are formed, they are capped by depositing another layer of material. In this manner, the newly porous layer is protected from direct exposure to the pressure of subsequent planarization processes. In alternative embodiments, the processes described herein are applied to introduce pores into a pre-formed layer of semiconductor to produce a porous semiconductor layer.
摘要翻译： 通过在致密电介质的预先形成的层中引入小的垂直或柱状间隙来产生多孔电介质层。 可以通过与用于在VLSI器件上形成金属线和其它特征的工艺不同的特殊工艺形成孔。 此外，在特定层的平坦化处理已经完成之后可以产生柱状间隙。 然后，在形成孔之后，通过沉积另一层材料来封盖它们。 以这种方式，保护新的多孔层免于直接暴露于随后的平坦化工艺的压力。 在替代实施例中，应用本文所述的工艺以将孔引入预成形的半导体层中以产生多孔半导体层。
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公开(公告)号：US06365451B2
公开(公告)日：2002-04-02
申请号：US09821602
申请日：2001-03-29
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L218238
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/1004 , H01L29/7322
摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.
摘要翻译： 一种制造半导体器件和器件的方法。 该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。 第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。 形成接触第二侧壁间隔物并与衬底隔开的导电区域。 第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。 开口填充有导电材料以将导电材料电耦合到基底。
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公开(公告)号：US06271577B1
公开(公告)日：2001-08-07
申请号：US09212136
申请日：1998-12-15
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L27082
CPC分类号： H01L29/66287 , H01L29/0821 , H01L29/1004 , H01L29/7322
摘要： A method of fabricating a semiconductor device and the device. The device is fabricated by providing a substrate having a region thereover of electrically conductive material, and a dielectric first sidewall spacer on the region of electrically conductive material. A second sidewall spacer is formed over the first sidewall spacer extending to the substrate from a material which is selectively removal relative to the first sidewall spacer. An electrically conductive region is formed contacting the second sidewall spacer and spaced from the substrate. The second sidewall spacer is selectively removable to form an opening between the substrate and the electrically conductive region. The opening is filled with electrically conductive material to electrically couple the electrically conductive material to the substrate.
摘要翻译： 一种制造半导体器件和器件的方法。 该器件通过提供具有导电材料之上的区域的基底和在导电材料区域上的电介质第一侧壁间隔物来制造。 第二侧壁间隔件形成在从相对于第一侧壁间隔件选择性地移除的材料延伸到基板的第一侧壁间隔物的上方。 形成接触第二侧壁间隔物并与衬底隔开的导电区域。 第二侧壁间隔件可选择性地移除以在基板和导电区域之间形成开口。 开口填充有导电材料以将导电材料电耦合到基底。
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9.发明授权Method of making an interconnect structure with an integrated low density dielectric 失效制造具有集成低密度电介质的互连结构的方法
公开(公告)号：US5488015A
公开(公告)日：1996-01-30
申请号：US246432
申请日：1994-05-20
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/441 , H01L21/469
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02359 , H01L21/31695 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10S148/043 , Y10S148/118
摘要： This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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10.发明授权
公开(公告)号：US5403759A
公开(公告)日：1995-04-04
申请号：US955942
申请日：1992-10-02
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： H01L21/768 , H01L27/11 , H01L21/265
CPC分类号： H01L27/1108 , H01L21/76889 , H01L21/76895 , Y10S257/903
摘要： A method of fabricating a transistor on a wafer including; forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.
摘要翻译： 一种在晶片上制造晶体管的方法，包括： 在绝缘体34的顶部上形成掺杂晶体管体42; 晶体管体中的掺杂源极/漏极区域; 在晶体管本体的顶部形成栅极氧化物44; 沿着晶体管本体形成侧壁间隔物; 在所述晶体管本体上沉积金属层; 在所述金属层上形成非晶硅层，所述非晶硅层以栅极和局部互连配置构图; 退火以在晶体管体内的源极/漏极区之上形成硅化物区域，并且其中金属层与非晶硅层反应以产生硅化栅极50和硅化局部互连50; 并且蚀刻金属层的非硅化部分以留下硅化物源极/漏极区域，硅化栅极和硅化局部互连。
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