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公开(公告)号：US4570220A
公开(公告)日：1986-02-11
申请号：US555027
申请日：1983-11-25
申请人： Raymond S. Tetrick , John Beaston , Robert L. Farrell , Alireza Sarabi , Sudarshan Balachandran , Edwin L. Jacks, Jr. , Steven D. Kassel
发明人： Raymond S. Tetrick , John Beaston , Robert L. Farrell , Alireza Sarabi , Sudarshan Balachandran , Edwin L. Jacks, Jr. , Steven D. Kassel
IPC分类号： G06F13/374 , G06F13/376 , G06F13/42 , G06F15/16
CPC分类号： G06F13/4243 , G06F13/374 , G06F13/376 , G06F13/4217 , G06F13/4239
摘要： A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devices (collectively referred to as "agents") to permit the exchange of data and messages at high speed using a minimum of "handshake" events prior to the actual data transfer. Both the serial and parallel bus protocals are controlled by message control means coupled to each communicating agent. A local bus is coupled to processing agents within the system such that local memory and secondary processing resources may be accessed without impacting data traffic along the parallel bus. Direct access to resources coupled to the local bus of an agent from other bus agents is also controlled by the message control means.
摘要翻译： 公开了一种用于在多个数据处理资源之间传送数据的多总线系统架构和改进的数据传输方法。 本发明的总线结构包括将数据处理单元和外围设备（统称为“代理”）互连的并行和串行总线，以允许使用最少的“握手”事件高速地交换数据和消息 在实际数据传输之前。 串行和并行总线原型都由耦合到每个通信代理的消息控制装置控制。 本地总线耦合到系统内的处理代理，使得可以访问本地存储器和二级处理资源而不影响沿着并行总线的数据业务。 由消息控制装置控制对来自其他总线代理的代理的本地总线的资源的直接访问。
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2.发明授权
公开(公告)号：US4807109A
公开(公告)日：1989-02-21
申请号：US6353
申请日：1987-01-14
CPC分类号： G06F13/4217
摘要： A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.
摘要翻译： 公开了一种用于耦合多处理器系统内的处理器的高速本地同步总线，使得可以访问本地存储器和辅助处理资源而不影响沿总线的数据业务。 本地总线采用消息控制方法和装置，其包括当处理资源正在响应请求时能够断言WAIT信号的能力。 通过置位WAIT信号，总线上的所有其他操作都将被延迟，直到传输完成。 使用WAIT信号使得能够以与主处理资源不同的速度工作的设备以与主处理资源的时钟速度同步的方式在总线上进行响应。
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公开(公告)号：US08205032B2
公开(公告)日：2012-06-19
申请号：US13069690
申请日：2011-03-23
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3851
摘要： Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.
摘要翻译： 公开了用于解码虚拟机控制结构标识的装置，方法和系统的实施例。 在一个实施例中，一种装置包括用于解码虚拟机控制结构标识数据的虚拟机控制结构。 虚拟机控制结构识别数据被解码成虚拟机控制结构字段的地址和偏移量。 补偿是帮助识别与要执行的虚拟机架构指令相关的微操作。
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公开(公告)号：US20110173613A1
公开(公告)日：2011-07-14
申请号：US13069690
申请日：2011-03-23
IPC分类号： G06F9/455
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3851
摘要： Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.
摘要翻译： 公开了用于解码虚拟机控制结构标识的装置，方法和系统的实施例。 在一个实施例中，一种装置包括用于解码虚拟机控制结构标识数据的虚拟机控制结构。 虚拟机控制结构识别数据被解码成虚拟机控制结构字段的地址和偏移量。 补偿是帮助识别与要执行的虚拟机架构指令相关的微操作。
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公开(公告)号：US20100031268A1
公开(公告)日：2010-02-04
申请号：US12221083
申请日：2008-07-31
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30087 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques are described that can be used to ensure ordered computation and/or retirement of threads in a multithreaded environment. Threads may contain bundled instances of work, each with unique ordering restrictions relative to other instances of work packaged in other threads in the system. When applied to 3D graphics, video and image processing domains allow unrestricted processing of threads until reaching their critical sections. Ordering may be required prior to executing critical sections and beyond.
摘要翻译： 描述了可用于确保多线程环境中线程的有序计算和/或退出的技术。 线程可能包含捆绑的工作实例，每个实例具有相对于系统中其他线程打包的其他工作实例的独特排序限制。 当应用于3D图形时，视频和图像处理域允许不受限制地处理线程直到到达其关键部分。 执行关键部分之前可能需要订购。
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6.发明授权公开(公告)号：US09035959B2
公开(公告)日：2015-05-19
申请号：US12057601
申请日：2008-03-28
申请人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
发明人： Zeev Offen , Ariel Berkovits , Thomas A. Piazza , Robert L. Farrell , Altug Koker , Opher Kahn
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0822 , G06F12/0828 , G06F12/0835 , G06F13/1668 , G06F13/28 , G06F13/4282 , G06F2212/283 , G06F2212/60 , G06F2212/621 , G06F2213/0026 , G06T1/60 , G11C7/1072
摘要： A technique to enable information sharing among agents within different cache coherency domains. In one embodiment, a graphics device may use one or more caches used by one or more processing cores to store or read information, which may be accessed by one or more processing cores in a manner that does not affect programming and coherency rules pertaining to the graphics device.
摘要翻译： 一种能够在不同高速缓存一致性域内的代理之间进行信息共享的技术。 在一个实施例中，图形设备可以使用由一个或多个处理核心使用的一个或多个高速缓存来存储或读取信息，这些信息可以由一个或多个处理核心以不影响与编程相关的编程和一致性规则的方式来访问 图形设备。
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公开(公告)号：US06785829B1
公开(公告)日：2004-08-31
申请号：US09608160
申请日：2000-06-30
申请人： Varghese George , Robert L. Farrell
发明人： Varghese George , Robert L. Farrell
IPC分类号： G06F132
CPC分类号： G06F1/3296 , G06F1/08 , G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.
摘要翻译： 一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。 这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。 结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。
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8.发明授权Integrating data scaling and buffering functions to minimize memory requirement 失效集成数据缩放和缓冲功能以最大限度地减少内存需求
公开(公告)号：US6091426A
公开(公告)日：2000-07-18
申请号：US887415
申请日：1997-07-03
IPC分类号： G09G5/00
CPC分类号： G06T3/4023
摘要： A scaling circuit residing on a single silicon substrate includes a buffer for storing a plurality of partially scaled data. A multiplier is provided for multiplying a weight signal with each of a plurality of input data to produce a plurality of weighted data. An adder is coupled to (1) the multiplier and (2) the buffer for adding each of the weighted data to one of the partially scaled data to produce a plurality of scaled data. When a first one of the scaled data is produced by the adder, the first one of the scaled data can remain in the buffer until displaced by a new data to be scaled such that the scaling circuit is directly coupled to an external bus without requiring any external buffering memory coupled in between. A method for scaling a block of data and transferring the scaled data to the bus is also described.
摘要翻译： 驻留在单个硅衬底上的缩放电路包括用于存储多个部分缩放的数据的缓冲器。 提供了一个乘法器，用于将加权信号与多个输入数据中的每一个相乘以产生多个加权数据。 加法器耦合到（1）乘法器和（2）用于将每个加权数据加到部分缩放数据之一中以产生多个缩放数据的缓冲器。 当加法器产生缩放数据中的第一个时，缩放数据中的第一个可以保留在缓冲器中，直到被要缩放的新数据移位，使得缩放电路直接耦合到外部总线，而不需要任何 耦合在其间的外部缓冲存储器。 还描述了用于缩放数据块并将缩放的数据传送到总线的方法。
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公开(公告)号：US5953411A
公开(公告)日：1999-09-14
申请号：US767360
申请日：1996-12-18
申请人： Robert L. Farrell
发明人： Robert L. Farrell
IPC分类号： H04M1/58
CPC分类号： H04M9/082
摘要： Input/output sample correlation is achieved through the use of first and second correlation tags appended to input and output buffers, respectively. As an output buffer of output samples is prepared, the first correlation tag identifies one of tie output samples in that buffer. As input samples are input and placed into an input buffer, a second correlation tag is appended to the input buffer which identifies the input sample that is input at the time the output sample identified by the first correlation tag is output. Accordingly, a correlation between input and output samples can be used in an echo cancellation operation or the like.
摘要翻译： 通过分别使用附加到输入和输出缓冲器的第一和第二相关标签来实现输入/输出样本相关。 当输出样本的输出缓冲器被准备好时，第一个相关标签识别该缓冲器中的一个输出样本。 当输入样本被输入并被放置到输入缓冲器中时，第二相关标签被附加到输入缓冲器，该输入缓冲器标识在输出由第一相关标签识别的输出样本时输入的输入样本。 因此，可以在回波消除操作等中使用输入和输出样本之间的相关性。
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10.发明授权Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path 失效用于基于微处理器的计算机系统的缓存子系统，具有同步和异步数据路径
公开(公告)号：US5293603A
公开(公告)日：1994-03-08
申请号：US710079
申请日：1991-06-04
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0835 , G06F12/0862 , G06F12/0897 , G06F2212/6082
摘要： An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for optimizing burst read and write operations to and from the CPU bus. These circuits allow a full cache line to be read or written in a single access of the SRAM array. Control logic is utilized within the CPU bus interface for controlling CPU bursts in the order defined by the CPU. The memory bus interface includes internal buffers used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparently passing data between the CPU and memory bus interfaces without disturbance of the SRAM array.
摘要翻译： 用作缓存子系统的集成电路实现了高速缓存静态随机存取存储器（SRAM）存储阵列，中央处理器单元（CPU）总线接口和主存储器总线接口。 CPU总线和主存储器总线接口包括多路复用器，缓冲器和本地控制，用于优化对CPU总线的突发读和写操作。 这些电路允许在SRAM阵列的单个访问中读取或写入完整的高速缓存行。 控制逻辑用于CPU总线接口，用于按照CPU定义的顺序控制CPU脉冲串。 存储器总线接口包括用于执行存储器总线读取，写入，回写和监听的内部缓冲器。 跟踪逻辑用于确定要用于特定存储器总线周期的适当的内部缓冲器。 另外，包括数据路径，用于在CPU和存储器总线接口之间透明地传递数据，而不会对SRAM阵列造成干扰。
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