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公开(公告)号：US5689151A
公开(公告)日：1997-11-18
申请号：US535506
申请日：1995-09-28
CPC分类号： H01J29/94 , H01J29/085 , H01J7/18 , H01J2201/30403 , H01J2329/00
摘要： An anode plate (10) for use in a field emission flat panel display device (8) comprises a transparent substrate (26) having a plurality of spaced-apart, electrically conductive regions (28) which form the anode electrode of the display device (8). The conductive regions (28) are covered by a luminescent material (24). A getter material (29) is deposited on the substrate (26) and between the conductive regions (28) of the anode plate (10). The getter material (29) is preferably an electrically nonconductive, high porosity, and low density material, such as an aerogel or xerogel. Methods of fabricating the getter material (29) on the anode plate (10) are disclosed.
摘要翻译： 一种用于场致发射平板显示装置（8）的阳极板（10）包括具有形成显示装置的阳极电极的多个间隔开的导电区域（28）的透明基板（26） 8）。 导电区域（28）被发光材料（24）覆盖。 吸气材料（29）沉积在衬底（26）上并在阳极板（10）的导电区域（28）之间。 吸气材料（29）优选是不导电，高孔隙率和低密度材料，例如气凝胶或干凝胶。 公开了在阳极板（10）上制造吸气材料（29）的方法。
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2.发明授权Porous dielectric material with a passivation layer for electronics applications 失效多孔电介质材料，具有电子应用的钝化层
公开(公告)号：US5661344A
公开(公告)日：1997-08-26
申请号：US476164
申请日：1995-06-07
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L51/00
CPC分类号： H01L21/02216 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L2221/1047 , H01L2924/0002
摘要： A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 31 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 14 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
摘要翻译： 公开了一种半导体器件及其制造方法，其使用多孔介电材料来减小导体之间的电容，同时允许常规光刻和金属技术和材料用于制造。 在一种结构中，图案化导体18设置在层间电介质10上，基底封装层31保形地沉积在该结构上。 然后沉积一层多孔电介质材料22（例如干燥的SiO 2凝胶）以基本上填充导体之间的间隙并且还覆盖导体。 然后沉积诸如SiO 2的材料的基本上固体的盖层14，然后沉积光刻步骤以限定通孔位置。 通孔通过盖层蚀刻，然后通过多孔电介质。 通孔钝化层30被共形沉积，然后各向异性蚀刻以清除通孔的底部，同时在通孔中留下钝化衬垫，防止通孔金属直接接触多孔材料。 可以使用这些步骤的第二应用来形成图案化导体38，封装层36，多孔介电层40和盖层42的第二覆盖结构。
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3.发明授权Porous composites as a low dielectric constant material for electronics applications 失效多孔复合材料作为用于电子应用的低介电常数材料
公开(公告)号：US5561318A
公开(公告)日：1996-10-01
申请号：US477029
申请日：1995-06-07
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L21/3121 , H01L2221/1047 , H01L2924/0002
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。 该方法可以包括在导体24之间和之上施加和凝胶化一种或多种溶液并干燥湿凝胶以产生至少多孔介电子层28和29.通过改变溶液的组成，胶凝条件，干燥温度，溶剂的组成 在湿凝胶中，或这些方法的组合，子层的孔隙率可以单独定制。 无孔介电层30可以形成在多孔层28之上，多孔层28可以完成层间电介质。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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4.发明授权Porous dielectric material with improved pore surface properties for electronics applications 失效多孔电介质材料，具有改进的孔表面性能，适用于电子应用
公开(公告)号：US6140252A
公开(公告)日：2000-10-31
申请号：US72905
申请日：1998-05-05
申请人： Chih-Chen Cho , Bruce E. Gnade , Douglas M. Smith , Jin Changming , William C. Ackerman , Gregory C. Johnston
发明人： Chih-Chen Cho , Bruce E. Gnade , Douglas M. Smith , Jin Changming , William C. Ackerman , Gregory C. Johnston
IPC分类号： H01L21/768 , H01L21/316 , H01L21/469 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5329 , H01L21/7682 , H01L23/5222 , H01L2221/1047 , H01L2924/0002
摘要： This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The method may comprise providing a substrate comprising a microelectronic circuit and a porous silica layer, the porous silica layer having an average pore diameter between 2 and 80 nm; and heating the substrate to one or more temperatures between 100 and 490 degrees C. in a substantially halogen-free atmosphere, whereby one or more dielectric properties of the porous dielectric are improved. In some embodiments, the atmosphere comprises a phenyl-containing atmosphere, such as hexaphenyldisilazane. In some embodiments, the method further comprises cooling the substrate and exposing the substrate to a substantially halogen-free atmosphere comprising either a phenyl-containing compound, such as hexaphenyldisilazane; or a methyl-containing compound, such as hexamethyldisilazane. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.
摘要翻译： 本发明提供一种用于半导体器件的改进的多孔结构及其制造方法。 该方法可以应用于可以例如在图案化导体24之间沉积的现有多孔结构28.该方法可以包括提供包括微电子电路和多孔二氧化硅层的基底，多孔二氧化硅层具有平均孔 直径在2和80nm之间; 并在基本上无卤素的气氛中将衬底加热至100至490摄氏度之间的一个或多个温度，从而提高多孔电介质的一种或多种介电性能。 在一些实施方案中，气氛包含含苯基的气氛，例如六苯基二硅氮烷。 在一些实施方案中，该方法还包括冷却基底并将基底暴露于基本上无卤素的气氛中，该气氛包含含苯基的化合物，例如六苯基二硅氮烷; 或含甲基的化合物，例如六甲基二硅氮烷。 已经发现，以这种方式处理的多孔结构通常相对于未处理的样品表现出改善的介电性能。
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公开(公告)号：US5804508A
公开(公告)日：1998-09-08
申请号：US735758
申请日：1996-10-23
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3121 , H01L21/3122 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L21/76834 , H01L2221/1047
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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6.发明授权Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications 失效用于形成多孔复合材料作为具有不同孔隙分布电子应用的低介电常数层的方法
公开(公告)号：US5494858A
公开(公告)日：1996-02-27
申请号：US255157
申请日：1994-06-07
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/469
CPC分类号： H01L21/7682 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L21/3121 , H01L2221/1047 , H01L2924/0002
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。 该方法可以包括在导体24之间和之上施加和凝胶化一种或多种溶液并干燥湿凝胶以产生至少多孔介电子层28和29.通过改变溶液的组成，胶凝条件，干燥温度，溶剂的组成 在湿凝胶中，或这些方法的组合，子层的孔隙率可以单独定制。 无孔介电层30可以形成在多孔层28之上，多孔层28可以完成层间电介质。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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7.发明授权Method of making an interconnect structure with an integrated low density dielectric 失效制造具有集成低密度电介质的互连结构的方法
公开(公告)号：US5488015A
公开(公告)日：1996-01-30
申请号：US246432
申请日：1994-05-20
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L21/441 , H01L21/469
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02359 , H01L21/31695 , H01L21/7682 , H01L21/76829 , H01L21/76834 , H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , Y10S148/043 , Y10S148/118
摘要： This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供了一种半导体器件及其制造方法，其显着降低了相邻导体之间的电容，以及强调机械强度，蚀刻兼容性和良好热传递的层间电介质结构。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质，并提供机械强度，热传递和用于通孔蚀刻的固体层。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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8.发明授权Method of making a semiconductor device using a low dielectric constant material 失效使用低介电常数材料制造半导体器件的方法
公开(公告)号：US5470802A
公开(公告)日：1995-11-28
申请号：US247195
申请日：1994-05-20
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： C04B38/00 , H01L21/312 , H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/02
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/3121 , H01L21/3122 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L21/76834 , H01L2221/1047
摘要： This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.
摘要翻译： 本发明提供一种在相邻导体之间制造具有降低的电容的半导体器件的方法。 该方法可以包括在导体24之间施加溶液，然后将溶液凝胶化，表面改性和干燥以形成极其多孔的介电层28.多孔介质层30可形成在多孔层28之上，多孔层28可以完成 层间电介质。 公开了一种用于产生多孔介电层的新方法，其可以在真空或环境压力下完成，但是在干燥期间导致电介质的孔隙率，孔径和收缩相当于仅通过在超临界压力下干燥凝胶可获得的电介质层。
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公开(公告)号：US5750415A
公开(公告)日：1998-05-12
申请号：US250747
申请日：1994-05-27
申请人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
发明人： Bruce E. Gnade , Chih-Chen Cho , Douglas M. Smith
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L21/76834 , H01L2924/0002
摘要： A method for forming air gaps 22 between metal leads 16 of a semiconductor device. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16, exposing portions of the substrate 12. A disposable liquid 18 is deposited on the metal leads 16 and the exposed portions of substrate 12, and a top portion of the disposable liquid 18 is removed to lower the disposable liquid 18 to at least the tops of the leads 16. A porous silica precursor film 20 is deposited on the disposable liquid 18 and over the tops of the leads 16. The porous silica precursor film 20 is gelled to form a low-porosity silica film 24. The disposable liquid 18 is removed through the low-porosity silica film 24 to form air gaps 22 between metal leads 16 beneath the low-porosity silica film 24. The air gaps 22 have a low dielectric constant and result in reduced capacitance between the metal leads and decreased power consumption.
摘要翻译： 一种用于在半导体器件的金属引线16之间形成气隙22的方法。 金属层沉积在基底12上。金属层被蚀刻以形成金属引线16，暴露基底12的部分。一次性液体18沉积在金属引线16和基底12的暴露部分上，顶部 去除一次性液体18的一部分以将一次性液体18降低到至少引线16的顶部。多孔二氧化硅前体膜20沉积在一次性液体18上并在引线16的顶部上。多孔二氧化硅前体 膜20凝胶化以形成低孔隙率二氧化硅膜24.一次性液体18通过低孔隙率二氧化硅膜24去除，以在低孔隙率二氧化硅膜24下面的金属引线16之间形成气隙22。气隙22 具有低介电常数，并且导致金属引线之间的电容降低并降低功耗。
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10.发明授权Method of fabricating porous dielectric material with a passivation layer for electronics applications 失效制造具有用于电子应用的钝化层的多孔电介质材料的方法
公开(公告)号：US5472913A
公开(公告)日：1995-12-05
申请号：US286761
申请日：1994-08-05
IPC分类号： H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532
CPC分类号： H01L21/02216 , H01L21/02126 , H01L21/02203 , H01L21/02282 , H01L21/02304 , H01L21/02337 , H01L21/02343 , H01L21/02359 , H01L21/02362 , H01L21/31695 , H01L21/76802 , H01L21/7682 , H01L21/76829 , H01L21/76831 , H01L23/5222 , H01L23/53223 , H01L2221/1047 , H01L2924/0002
摘要： A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric. A via passivating layer 30 is conformally deposited and then anisotropically etched to clear the bottom of the vias while leaving a passivating liner in the via, preventing the via metal from directly contacting the porous material. A second application of these steps may be used to form a second, overlying structure of patterned conductors 38, encapsulating layer 36, porous dielectric layer 40, and cap layer 42.
摘要翻译： 公开了一种半导体器件及其制造方法，其使用多孔介电材料来减小导体之间的电容，同时允许常规光刻和金属技术和材料用于制造。 在一个结构中，图案化导体18设置在层间电介质10上，基底封装层32保形地沉积在该结构上。 然后沉积一层多孔电介质材料22（例如干燥的SiO 2凝胶）以基本上填充导体之间的间隙并且还覆盖导体。 然后沉积诸如SiO 2的材料的基本上固体的盖层24，然后沉积光刻步骤以限定通孔位置。 通孔通过盖层蚀刻，然后通过多孔电介质。 通孔钝化层30被共形沉积，然后各向异性蚀刻以清除通孔的底部，同时在通孔中留下钝化衬垫，防止通孔金属直接接触多孔材料。 可以使用这些步骤的第二应用来形成图案化导体38，封装层36，多孔介电层40和盖层42的第二覆盖结构。
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