公开(公告)号：US5977960A

公开(公告)日：1999-11-02

申请号：US707937

申请日：1996-09-10

申请人： Robert Marshall Nally ,  John C. Schafer

发明人： Robert Marshall Nally ,  John C. Schafer

IPC分类号： G09G5/14 ,  G09G5/395 ,  G09G5/36

CPC分类号： G09G5/395 ,  G09G5/14 ,  G09G2340/125

摘要： A memory system 107,300 is provided which includes a memory 107 having a data area for storing data words and a mask area 302 for storing a control mask. Mask generation circuitry 301 is provided for generating such a control mask for storage in the mask area 302 of the memory 107. Mask controlled memory read control circuitry 303 is provided which is operable to selectively retrieve from the mask area 302 bits of the mask stored therein and in response selectively retrieve and output data words stored in the data area of the memory 107.

摘要翻译： 提供了一种存储器系统107,300，其包括具有用于存储数据字的数据区域的存储器107和用于存储控制掩码的掩码区域302。 掩膜产生电路301被提供用于产生用于存储在存储器107的掩模区域302中的这种控制掩模。提供了掩模控制的存储器读取控制电路303，其可操作以从掩模区域选择性地检索存储在其中的掩模的302位 并且响应于选择性地检索和输出存储在存储器107的数据区域中的数据字。

公开(公告)号：US20140055559A1

公开(公告)日：2014-02-27

申请号：US13568875

申请日：2012-08-07

申请人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

发明人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

IPC分类号： G06T15/00 ,  H04N13/00

CPC分类号： G06T15/005 ,  G06F15/78 ,  G09G5/003 ,  G09G2360/02 ,  H04N13/161

摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

摘要翻译： 为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。 这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。 在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如 作为电视机，显示器和网络设备，如打印机和网络录像机。 本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。 该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。 在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

公开(公告)号：US5402513A

公开(公告)日：1995-03-28

申请号：US266164

申请日：1994-06-27

申请人： John C. Schafer

发明人： John C. Schafer

IPC分类号： G06T3/40 ,  G09G5/14 ,  G06K9/36

CPC分类号： G06T3/4007 ,  G09G5/14 ,  G09G2340/125

摘要： A pixel processor is disclosed which is comprised of a video window generator (VWG) (10). VWG (10) utilizes a conversion section for receiving an input video signal in a YUV 422 video format and converting it to an RGB video format. The conversion section includes a chroma interpolator 56 for converting the YUV 422 video format to a YUV 444 video format, a color converter (58) for converting the YUV 444 video format to an RGB video format, and then to a gamma coding removal block (60) for removing gamma coding. After conversion, the RGB video format signal is then scaled down by a linear resampler block (62) to average information over a predetermined portion of the input display space for output to a predetermined portion of the output display space. The scaled video output is truncated by a quantization processor (64) and then input to a FIFO (66). A control unit (68) controls the operation of the system. The linear resampler circuit (68) is an interpolation filter for averaging the information of a number of pixels disposed about a point in the input display space that is to be mapped into a point in the output display space. The point in the output display space is comprised of a pixel. The interpolation filer operates on pixels disposing in an adjacent relationship within a row of pixels within an input array. If the point to be mapped into the output display space falls between two pixels, the weighted average is taken between the two adjacent pixels. Rows of pixels are selected in accordance with the nearest neighbor algorithm. The quantization processor (64) is operable to truncate a predetermined number of bits from each word in each of the color planes in the output data prior to outputting the data. The truncated data is then utilized as an error which is added to the value of the next pixel before truncation thereof.

摘要翻译： 公开了一种由视频窗口发生器（VWG）（10）组成的像素处理器。 VWG（10）利用转换部分接收YUV 422视频格式的输入视频信号并将其转换为RGB视频格式。 转换部分包括用于将YUV 422视频格式转换为YUV 444视频格式的色度内插器56，用于将YUV 444视频格式转换为RGB视频格式的颜色转换器（58），然后到伽马编码移除块（ 60）用于去除伽马编码。 在转换之后，然后通过线性重采样器块（62）将RGB视频格式信号缩小以在输入显示空间的预定部分上平均信息，以输出到输出显示空间的预定部分。 缩放视频输出被量化处理器（64）截断，然后输入到FIFO（66）。 控制单元（68）控制系统的操作。 线性重采样电路（68）是用于对要被映射到输出显示空间中的点的输入显示空间中的点周围的多个像素的信息进行平均的内插滤波器。 输出显示空间中的点由像素组成。 插值滤波器对输入阵列内的像素行内的相邻关系中的像素进行操作。 如果要映射到输出显示空间的点落在两个像素之间，则在两个相邻像素之间采用加权平均。 根据最近邻算法选择像素行。 量化处理器（64）可操作以在输出数据之前在输出数据中的每个色平面中的每个字节中截断预定数量的位。 然后将截断的数据用作在其截断之前添加到下一个像素的值的错误。

公开(公告)号：US5402506A

公开(公告)日：1995-03-28

申请号：US265496

申请日：1994-06-23

申请人： John C. Schafer

发明人： John C. Schafer

IPC分类号： G06T9/00 ,  G09G5/02 ,  G09G5/14 ,  G06K9/38

CPC分类号： G09G5/14 ,  G06T9/005 ,  G09G5/02 ,  G09G2340/125

摘要： A quantization processor (64) is provided that is operable to provide an error diffusion for adjacent output pixels in an output display space. Three quantization processors (300), (302) and (304) are provided for the three colors of the video RGB format. A full adder (312) is provided for receiving both an error signal and an input pixel value. The composite output is input to an input/output error register 328 that is operable to store bits of the output of the adder, determined to be output bits, and also to store the remainder of the bits that are determined to be error or truncated bits. The error or truncated bits are fed back to the input of the full adder. A rounding decoder (306) is operable to receiving a masking word, such that the outputs from the register (326) are either selected as bits to be truncated, provide an error to be added to the next sequential pixel value, or they are selected as outputs. The register (326) is operable to store the error bits for the next sequential cycle.

摘要翻译： 提供了一种量化处理器（64），其可操作以向输出显示空间中的相邻输出像素提供误差扩散。 为视频RGB格式的三种颜色提供三个量化处理器（300），（302）和（304）。 提供全加器（312）用于接收误差信号和输入像素值。 复合输出被输入到输入/输出错误寄存器328，其可操作以存储被确定为输出位的加法器的输出的位，并且还存储确定为错误或截断位的位的剩余部分 。 错误或截断的位反馈到全加器的输入。 舍入解码器（306）可操作以接收掩蔽字，使得来自寄存器（326）的输出被选择为要被截断的位，提供要添加到下一个顺序像素值的错误，或者它们被选择 作为输出。 寄存器（326）可操作以存储下一个连续周期的错误位。

公开(公告)号：USRE39898E1

公开(公告)日：2007-10-30

申请号：US09374041

申请日：1999-08-13

申请人： Robert M. Nally ,  John C. Schafer

发明人： Robert M. Nally ,  John C. Schafer

IPC分类号： G09G5/397 ,  G09G5/36 ,  G09G5/39 ,  G06F15/80 ,  G06F15/76 ,  G06T1/20

CPC分类号： G06T11/203

摘要： A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

摘要翻译： 提供了图形和视频控制器105，其包括用于接收图形和视频像素数据的单词的双孔径接口206，这些数据的每个单词与将要处理的字作为图形或视频数据相关联的地址相关联。 电路200,201,202,207,208被提供用于将从接口206接收的像素数据的字写入对应于与接收到的字相关联的地址的开和关屏幕之间的存储区域中的一个。 提供电路201,202用于从屏幕上和离屏存储区域选择性地检索图形和视频数据。 提供第一流水线205，用于处理从帧缓冲器107的屏幕上区域接收的数据，同时提供第二流水线204用于处理从帧缓冲器的屏幕外区域检索的数据。

公开(公告)号：US5581280A

公开(公告)日：1996-12-03

申请号：US402931

申请日：1995-03-13

申请人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

发明人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/36 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G5/40 ,  H04N9/64

CPC分类号： H04N9/641 ,  G09G5/006 ,  G09G5/008 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/40 ,  G09G2310/0232 ,  G09G2320/0606 ,  G09G2320/0673 ,  G09G2340/0407 ,  G09G2340/125

摘要： A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

摘要翻译： 提供显示接口装置20，其包括用于接收视频数据字的输入，视频数据字包括用于控制显示器的输出格式的控制代码和从相关视频控制器接收的视频时钟信号。 先进先出存储器30还具有通过第一时钟定时存入存储器30的视频数据字，并通过从相关图形控制器接收的时钟产生的第二时钟从存储器30中输出。

公开(公告)号：US5506604A

公开(公告)日：1996-04-09

申请号：US223845

申请日：1994-04-06

申请人： Robert M. Nally ,  John C. Schafer ,  Jeffrey A. Niehaus

发明人： Robert M. Nally ,  John C. Schafer ,  Jeffrey A. Niehaus

IPC分类号： G09G5/39 ,  H04N9/64 ,  H04N11/20 ,  G09G5/04

CPC分类号： G09G5/39 ,  H04N11/20 ,  H04N9/641 ,  G09G2340/0407 ,  G09G2340/125

摘要： A processing system 100 is provided which includes a memory 107 and memory control circuitry 203. Packing circuitry 215 is operable to receive a stream of video data words in a first YUV format and convert those video data words into a plurality of packed words in a second YUV format. Memory control circuitry 203 is operable to simultaneously store the plurality of packed YUV words in memory 107 in the second format along with a plurality of RGB words.

摘要翻译： 提供了一种处理系统100，其包括存储器107和存储器控制电路203.打包电路215可操作以接收第一YUV格式的视频数据字流，并将这些视频数据字转换为多个打包字 YUV格式。 存储器控制电路203可操作以将多个打包的YUV字与多个RGB字同时存储在第二格式的存储器107中。

公开(公告)号：US08253750B1

公开(公告)日：2012-08-28

申请号：US12832830

申请日：2010-07-08

申请人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

发明人： Jen-Hsun Huang ,  Gerrit A. Slavenburg ,  Stephen D. Lew ,  John C. Schafer ,  Thomas F. Fox ,  Taner E. Ozcelik

IPC分类号： G06F13/14 ,  G06F15/80 ,  G06F15/00

CPC分类号： G06T15/005 ,  G06F15/78 ,  G09G5/003 ,  G09G2360/02 ,  H04N13/161

摘要： Circuits, methods, and apparatus that provide highly integrated digital media processors for digital consumer electronics applications. These digital media processors are capable of performing the parallel processing of multiple format audio, video, and graphics signals. In one embodiment, audio and video signals may be received from a variety of input devices or appliances, such as antennas, VCRs, DVDs, and networked devices such as camcorders and modems, while output audio and video signals may be provided to output devices such as televisions, monitors, and networked devices such as printers and networked video recorders. Another embodiment of the present invention interfaces with a variety of devices such as navigation, entertainment, safety, memory, and networking devices. This embodiment can also be configured for use in a digital TV, set-top box, or home server. In this configuration, video and audio streams may be received from a number of cable, satellite, Internet, and consumer devices.

摘要翻译： 为数字消费电子应用提供高度集成的数字媒体处理器的电路，方法和设备。 这些数字媒体处理器能够执行多格式音频，视频和图形信号的并行处理。 在一个实施例中，音频和视频信号可以从诸如天线，VCR，DVD以及诸如摄像机和调制解调器之类的网络设备的各种输入设备或设备接收，而输出音频和视频信号可以被提供给诸如 作为电视机，显示器和网络设备，如打印机和网络录像机。 本发明的另一实施例与诸如导航，娱乐，安全，存储器和网络设备的各种设备接口。 该实施例还可以被配置为用于数字电视，机顶盒或家庭服务器中。 在该配置中，可以从多个有线，卫星，因特网和消费者设备接收视频和音频流。

公开(公告)号：US5625379A

公开(公告)日：1997-04-29

申请号：US402935

申请日：1995-03-13

申请人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

发明人： Christopher L. Reinert ,  Sudhir Sharma ,  Robert M. Nally ,  John C. Schafer

IPC分类号： G09G3/20 ,  G09G5/00 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/36 ,  G09G5/391 ,  G09G5/395 ,  G09G5/399 ,  G09G5/40 ,  H04N9/64 ,  G09G5/04

CPC分类号： H04N9/641 ,  G09G5/006 ,  G09G5/008 ,  G09G5/02 ,  G09G5/06 ,  G09G5/08 ,  G09G5/363 ,  G09G5/391 ,  G09G5/395 ,  G09G5/40 ,  G09G2310/0232 ,  G09G2320/0606 ,  G09G2320/0673 ,  G09G2340/0407 ,  G09G2340/125

摘要： A display interface device 20 is provided which includes inputs for receiving video data words, the video data words including control codes for controlling the output format of a display, and a video clock signal received from an associated video controller. A first-in/first-out memory 30 is also provided with a video data word clocked into memory 30 by the first clock and clocked out of memory 30 by a second clock generated from a clock received from an associated graphics controller.

摘要翻译： 提供显示接口装置20，其包括用于接收视频数据字的输入，视频数据字包括用于控制显示器的输出格式的控制代码和从相关视频控制器接收的视频时钟信号。 先进先出存储器30还具有通过第一时钟定时存入存储器30的视频数据字，并通过从相关图形控制器接收的时钟产生的第二时钟从存储器30中输出。

公开(公告)号：US5598525A

公开(公告)日：1997-01-28

申请号：US376919

申请日：1995-01-23

申请人： Robert M. Nally ,  John C. Schafer

发明人： Robert M. Nally ,  John C. Schafer

IPC分类号： G06T11/20 ,  G06F15/00

CPC分类号： G06T11/203

摘要： A graphics and video controller 105 is provided which includes a dual aperture interface 206 for receiving words of graphics and video pixel data, each word of such data associated with an address directing that word to be processed as either graphics or video data. Circuitry 200, 201, 202, 207, 208 is provided for writing a word of the pixel data received from the interface 206 to a one of the on- and off-screen memory areas corresponding to the address associated with the received word. Circuitry 201, 202 is provided for selectively retrieving graphics and video data from the on-screen and off-screen memory areas. A first pipeline 205 is provided for processing data received from the on-screen area of frame buffer 107 while a second pipeline 204 is provided for processing data retrieved from the off-screen area of the frame buffer.

摘要翻译： 提供了图形和视频控制器105，其包括用于接收图形和视频像素数据的单词的双孔径接口206，这些数据的每个单词与将要处理的字作为图形或视频数据相关联的地址相关联。 提供电路200,201,202,207,208，用于将从接口206接收的像素数据的字写入对应于与接收到的字相关联的地址的开和关屏幕之间的存储区域中的一个。 提供电路201,202用于从屏幕上和离屏存储区域选择性地检索图形和视频数据。 提供第一流水线205，用于处理从帧缓冲器107的屏幕上区域接收的数据，同时提供第二流水线204用于处理从帧缓冲器的屏幕外区域检索的数据。