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公开(公告)号：US07260704B2
公开(公告)日：2007-08-21
申请号：US10164345
申请日：2002-06-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F12/0862 , G06F2212/6026 , G06F2212/6028
摘要： A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.
摘要翻译： 具有预取链增强机制的内容预取器。 响应于预取链中的高速缓存线上的预取命中，提升命中高速缓存行的请求深度并扫描命中高速缓存行用于候选虚拟地址，以便加强预取链。
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公开(公告)号：US06954840B2
公开(公告)日：2005-10-11
申请号：US09999518
申请日：2001-11-30
CPC分类号： G06F12/0862 , G06F2212/6026 , G06F2212/6028
摘要： A content prefetcher including a virtual address predictor. The virtual address predictor identifies candidate virtual addresses in a cache line without reference to an external address source.
摘要翻译： 包含虚拟地址预测器的内容预取器。 虚拟地址预测器识别高速缓存行中的候选虚拟地址，而不引用外部地址源。
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3.发明授权Method and apparatus for identifying candidate virtual addresses in a content-aware prefetcher 有权用于识别内容感知预取器中的候选虚拟地址的方法和装置公开(公告)号：US06675280B2
公开(公告)日：2004-01-06
申请号：US10000549
申请日：2001-11-30
IPC分类号： G06F1200
CPC分类号： G06F12/0897 , G06F12/0215 , G06F12/0862 , G06F2212/6028
摘要： A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.
摘要翻译： 一种用于识别高速缓存线中的虚拟地址的方法和装置。 为了区分候选虚拟地址与数据值和随机位模式，将高速缓存行中的地址大小的字的高位与高速缓存行的有效地址的高位进行比较。 如果地址大小字的高位匹配有效地址的高位，那么将地址大小的字识别为候选虚拟地址。
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公开(公告)号：US07093077B2
公开(公告)日：2006-08-15
申请号：US10163977
申请日：2002-06-05
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/6026 , G06F2212/6028
摘要： A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.
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公开(公告)号：US20110060931A1
公开(公告)日：2011-03-10
申请号：US12557263
申请日：2009-09-10
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128 , Y02D50/20
摘要： A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.
摘要翻译： 一种能够以各种模式对片上系统进行功率测量的方法和系统。 在本发明的一个实施例中，片上系统具有其逻辑和电路的完全可控性，以便于将片上系统配置成期望的操作模式。 这允许钩子或接口在外部访问片上系统进行测量。 例如，在本发明的一个实施例中，片上系统中的钩子允许后端测试器将片上系统配置成各种模式，以便简单地执行系统级芯片的一个或多个单独部件的功耗测量， 片上 片上系统中各个组件的功耗测量可以更快地执行，并且可以更准确。 另外，由于易于检测故障部件，所以能够提高SOC的整体产量。
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6.发明授权Decoupling the number of logical threads from the number of simultaneous physical threads in a processor 有权从处理器中同时处理的物理线程的数量解耦逻辑线程数公开(公告)号：US07797683B2
公开(公告)日：2010-09-14
申请号：US10745527
申请日：2003-12-29
申请人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
发明人： Per H. Hammarlund , Stephan J. Jourdan , Pierre Michaud , Alexandre J. Farcy , Morris Marden , Robert L. Hinton , Douglas M. Carmean
IPC分类号： G06F9/44
CPC分类号： G06F9/485 , G06F9/3851
摘要： Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.
摘要翻译： 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个维持在等待状态，活动状态，排出状态和失速状态之一。 可以使用状态机和硬件定序器来基于触发事件来转换状态之间的逻辑线程，以及是否在逻辑线程中遇到可中断点。 逻辑线程被安排在物理线程上以满足例如优先级，性能或公平性目标。 也可以指定每个逻辑线程可用的资源，以满足这些目标和其他目标。 在一个示例中，单个逻辑线程可以推测使用多个物理线程，等待选择要提交哪个物理线程。
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公开(公告)号：US07644236B2
公开(公告)日：2010-01-05
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译： 提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。 存储器缓存库预测单元具有接收指令的输入端口。 存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。
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公开(公告)号：US07502912B2
公开(公告)日：2009-03-10
申请号：US10749272
申请日：2003-12-30
IPC分类号： G06F9/38
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for rescheduling operations in a processor. More particularly, the present invention relates to optimally using a scheduler resource in a processor by analyzing, predicting, and sorting the write order of instructions into the scheduler so that the duration the instructions sit idle in the scheduler is minimized. The analyses, prediction, and sorting may be done between an instruction queue and a scheduler by using delay units. The prediction can be based on history (latency, dependency, and resource) or on a general prediction scheme.
摘要翻译： 一种用于在处理器中重新调度操作的方法和装置。 更具体地说，本发明涉及通过分析，预测和排序指令的写入顺序来最优化地使用处理器中的调度器资源，使得指令在调度器中空闲的持续时间最小化。 分析，预测和排序可以通过使用延迟单元在指令队列和调度器之间完成。 预测可以基于历史（延迟，依赖和资源）或一般预测方案。
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公开(公告)号：US07444457B2
公开(公告)日：2008-10-28
申请号：US10743285
申请日：2003-12-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F9/383 , G06F12/0864
摘要： Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.
摘要翻译： 处理地址的系统和方法提供用于接收指令的完整线性地址并减小全线性地址的大小以获得减小的线性地址。 如果减少的线性地址对应于标签阵列中的标签，其中标签阵列与数据阵列相关联，则可以从数据阵列检索数据块。 缩小的线性地址可使标签阵列的尺寸更小或实现增强的性能。 数据阵列可以是高速缓存的分支预测器或高速缓存阵列的预测阵列。
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10.发明授权Method and apparatus for predicting values in a processor having a plurality of prediction modes 失效用于预测具有多种预测模式的处理器中的值的方法和装置公开(公告)号：US07428627B2
公开(公告)日：2008-09-23
申请号：US09750150
申请日：2000-12-29
IPC分类号： G06F12/02
CPC分类号： G06F9/383 , G06F9/3455 , G06F9/3832 , G06F9/3844
摘要： A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP table includes a plurality of PIP information fields and the next value table includes a plurality of fields. The multi-mode predictor also includes a plurality of prediction modes. The processor includes a set of instructions that index the PIP table to provide a valid signal. The processor also includes a set of predicted values for the set of instructions. The set of predicted values is stored in the PIP table and the next value table. According to the valid signal a hit/miss condition in the next value table, a predicted value is selected from the PIP table or the next value table.
摘要翻译： 公开了一种具有多种预测模式的处理器的多模式预测器。 预测模式用于预测非二进制值。 预测器是包括每IP（“PIP”）表和下一个值表的多模式预测器。 PIP表包括多个PIP信息字段，下一个值表包括多个字段。 多模式预测器还包括多种预测模式。 处理器包括一组索引PIP表以提供有效信号的指令。 处理器还包括用于该组指令的一组预测值。 预测值的集合存储在PIP表和下一个值表中。 根据有效信号在下一个值表中的命中/未命中条件，从PIP表或下一个值表中选择预测值。
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