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1.发明授权Use of logic circuit embedded into comparator for foreground offset cancellation 有权使用嵌入到比较器中的逻辑电路进行前景偏移消除公开(公告)号：US08836549B2
公开(公告)日：2014-09-16
申请号：US13330939
申请日：2011-12-20
申请人： Robert Schell , Michael R. Elliott
发明人： Robert Schell , Michael R. Elliott
IPC分类号： H03M1/06
CPC分类号： H03M1/1061 , H03M1/167
摘要： A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.
摘要翻译： 这里描述了一种系统和方法，其提供了比较器在每个比较器的基础上的偏移的校准。 使用低功率DAC在确定的注入点对比较器进行注入，以校准比较器的偏移。 可以通过基于比较器的输出和比较器的偏移而产生的数字码字来选择性地控制DAC。 本发明的其它实施例提出了一种校准在流水线ADC的每个级中的闪存ADC的比较器的偏移的系统和方法。 该系统和方法可以以不影响流水线ADC的速度或向流水线ADC增加显着功率的方式提供校准。
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2.发明申请USE OF LOGIC CIRCUIT EMBEDDED INTO COMPARATOR FOR FOREGROUND OFFSET CANCELLATION 有权使用嵌入式比较器的逻辑电路进行前置取消公开(公告)号：US20130154860A1
公开(公告)日：2013-06-20
申请号：US13330939
申请日：2011-12-20
申请人： Robert Schell , Michael R. Elliott
发明人： Robert Schell , Michael R. Elliott
CPC分类号： H03M1/1061 , H03M1/167
摘要： A system and method are described herein that provide for the calibration of the offset of a comparator on a per-comparator basis. An injection is made to the comparator at determined injection points using a low-power DAC, to calibrate the offset of the comparator. The DAC can be selectively controlled by a digital codeword that is generated based on an output of the comparator and the comparator's offset. Further embodiments of the invention present a system and method for calibrating the offset of a comparator of a flash ADC in each stage of a pipeline ADC. The system and method may provide for the calibration in a manner without affecting the speed of the pipeline ADC or adding significant power to the pipeline ADC.
摘要翻译： 这里描述了一种系统和方法，其提供了比较器在每个比较器的基础上的偏移的校准。 使用低功率DAC在确定的注入点对比较器进行注入，以校准比较器的偏移。 可以通过基于比较器的输出和比较器的偏移而产生的数字码字来选择性地控制DAC。 本发明的其它实施例提出了一种校准在流水线ADC的每个级中的闪存ADC的比较器的偏移的系统和方法。 该系统和方法可以以不影响流水线ADC的速度或向流水线ADC增加显着功率的方式提供校准。
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公开(公告)号：US07623051B2
公开(公告)日：2009-11-24
申请号：US12150659
申请日：2008-04-29
IPC分类号： H03M1/10
CPC分类号： H03M1/0809 , H03M1/068 , H03M1/069 , H03M1/0863 , H03M1/164
摘要： Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.
摘要翻译： 提供了信号转换器系统，其减少了当模拟输入信号接近系统比较器的参考阈值Vth时通常发生的亚稳转换误差引起的系统误码率的降低。 当操作正确时，当输入信号越过阈值时，比较器产生相应的转换器代码。 然而，可调节性可能会导致比较器无法生成相应的转换器代码。 在系统实施例中，提供逻辑以在预定判定周期结束时感测到不存在比较器判定。 响应于这种缺失，系统被配置为替换相应的转换器代码。 在另一个实施例中，系统被配置为当它位于预定的数字代码窗口之外时替换对应的转换器代码。
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4.发明授权公开(公告)号：US06172636B2
公开(公告)日：2001-01-09
申请号：US09352828
申请日：1999-07-13
申请人： Frank Murden , Michael R. Elliott
发明人： Frank Murden , Michael R. Elliott
IPC分类号： H03M112
CPC分类号： H03M1/445
摘要： Structures and methods are provided that linearize and stabilize the gain of adjustable-gain folding amplifiers. Accordingly, these folding amplifiers are suited for use in various compound ADCs where they improve the performance of subsequent folding amplifier stages, increase the number of allowed subsequent stages and replace the functions of other portions of compound ADCs (e.g., subranging ADCs).
摘要翻译： 提供了可调节增益折叠放大器的线性化和稳定增益的结构和方法。 因此，这些折叠放大器适用于各种复合ADC，其中它们提高随后的折叠放大器级的性能，增加允许的后续级的数量并替代复合ADC的其它部分（例如，辅助ADC）的功能。
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5.发明授权Intermediate frequency (IF) sampling clock-to-clock auto-ranging analog-to-digital converter (ADC) and method 失效中频（IF）采样时钟到时钟自动量程模数转换器（ADC）和方法
公开(公告)号：US5861831A
公开(公告)日：1999-01-19
申请号：US772358
申请日：1996-12-23
CPC分类号： H03M1/186
摘要： A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.
摘要翻译： 时钟到时钟自动量程ADC直接在IF频带或更高的模拟信号上进行操作，以便在时钟基础上跟踪其增益范围，并产生数字信号，保持模拟信号的高分辨率，无需剪辑 或信号灵敏度损失。 这通过对具有足够高频率的模拟信号进行采样来实现，峰值检测器可以在至少半个信号周期上精确地确定最大信号电平，然后在下一个采样开始之前复位进入ADC的信号增益 期。 这确保模拟信号始终在ADC的范围内。 根据众所周知的抽样原理，采样模拟信号被混叠到DC与采样频率的一半之间的频率区域。
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公开(公告)号：US08547134B1
公开(公告)日：2013-10-01
申请号：US13556381
申请日：2012-07-24
IPC分类号： H03K17/16 , H03K19/003 , H03K19/094 , H03K3/00 , H03B1/00
CPC分类号： H04L25/0278
摘要： A system provides for a serial transmitter with multiplexing and driving functionality that is combined into a single stage to increase the overall speed of the serial transmitter. The single stage includes a dynamic impedance that is configured in parallel with a multiplexing driver to reduce the input capacitance and set the correct output impedance. The single stage can be implemented as a stacked or cross-coupled XOR logic circuit or a stacked or cross-coupled multiplexer (“mux”) as the multiplexing driver. In an embodiment where a mux is used as the multiplexing driver, a clock can be injected into the mux driver to overcome inter-symbol interference.
摘要翻译： 系统为串行发射机提供多路复用和驱动功能，将其组合成单级，以提高串行发射机的整体速度。 单级包括与多路复用驱动器并联配置的动态阻抗，以减少输入电容并设置正确的输出阻抗。 单级可以实现为堆叠或交叉耦合的异或逻辑电路或堆叠或交叉耦合多路复用器（“多路复用器”）作为多路复用驱动器。 在多路复用器被用作复用驱动器的实施例中，时钟可以被注入多路复用器驱动器以克服符号间干扰。
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公开(公告)号：US07974589B2
公开(公告)日：2011-07-05
申请号：US12069969
申请日：2008-02-13
IPC分类号： H04B1/02
CPC分类号： H04L25/0276 , H04L25/0278 , H04L25/028
摘要： Data transmitter embodiments are provided which are particularly useful as interface devices for accurate and reliable transmittal of data from high-speed data system devices such as analog-to-digital converters. Transmitter embodiments have been found to provide excellent fidelity of data transfer at high data rates (e.g., 4 gigabits/second) while consuming only a portion of the power of many conventional transmitters and requiring only a portion of the layout area of these transmitters. Transmitter embodiments provide effective control of transmitter parameters such as matched impedances, data symmetry, common-mode level, data eye and current drain.
摘要翻译： 提供了数据发射机实施例，其特别用作用于从诸如模数转换器之类的高速数据系统设备准确和可靠地传送数据的接口设备。 已经发现发射机实施例以高数据速率（例如，4千兆比特/秒）提供数据传输的出色保真度，同时仅消耗许多传统发射机的一部分功率，并且仅需要这些发射机的布局区域的一部分。 发射机实施例提供发射机参数的有效控制，例如匹配阻抗，数据对称性，共模电平，数据眼和电流消耗。
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8.发明授权Common-mode control structures and signal converter systems for use therewith 有权共模控制结构和与其一起使用的信号转换器系统公开(公告)号：US07405625B1
公开(公告)日：2008-07-29
申请号：US11789858
申请日：2007-04-25
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F3/45659 , H03F3/45677 , H03F3/45748 , H03F2200/513 , H03F2203/45052 , H03F2203/45074 , H03F2203/45354 , H03F2203/45442 , H03F2203/45636 , H03F2203/45652 , H03M1/1245 , H03M1/145
摘要： Control structures are provided to accurately maintain amplifier common-mode levels at the predetermined level of a common-mode reference voltage Vcm. The disclosed control structures provide amplifier feedback along a first feedback path that is configured to provide high gain and low bandwidth to closely maintain amplifier common-mode level at the predetermined level of a common-mode reference voltage Vcm. They also provide amplifier feedback along a second feedback path that is configured to provide wide bandwidth to substantially reduce perturbations of the common-mode level that would have otherwise been induced by input signal transients. In an important amplifier feature, these controls are obtained without use of structures (e.g., capacitors and switching transistors) that use substantial current which reduces amplifier efficiency. Although the disclosed control structures may be used in a variety of systems, they are particularly suited for use in samplers and converter stages of pipelined analog-to-digital converters.
摘要翻译： 提供控制结构以在共模参考电压V cm cm的预定电平下精确地保持放大器共模电平。 所公开的控制结构提供沿着第一反馈路径的放大器反馈，其被配置为提供高增益和低带宽，以在共模参考电压V cm的预定电平下紧密维持放大器共模电平。 。 它们还沿着第二反馈路径提供放大器反馈，其被配置为提供宽带宽以基本上减少否则由输入信号瞬变引起的共模电平的扰动。 在重要的放大器特征中，获得这些控制，而不使用使用降低放大器效率的大量电流的结构（例如，电容器和开关晶体管）。 尽管公开的控制结构可以用于各种系统，但是它们特别适用于流水线模数转换器的采样器和转换器级。
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9.发明授权Translators and methods for converting differential signals to single-ended signals 有权用于将差分信号转换为单端信号的转换器和方法公开(公告)号：US06191619B1
公开(公告)日：2001-02-20
申请号：US09382046
申请日：1999-08-24
IPC分类号： H03K19086
CPC分类号： H03K19/01812
摘要： High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced. Translator speed is further enhanced with elements associated with the current-diverting transistors that prevent saturation in the current mirrors and the complimentary output stage.
摘要翻译： 提供高速信号转换器以将差分输入信号（例如，ECL信号）转换为单端输出信号（例如，CMOS信号）。 示例性的翻译器由第一和第二电流镜，第一和第二互补差分晶体管对，互补晶体管输出级以及第一和第二电流转向晶体管形成。 辅助输出级最初产生单端输出信号，以响应从互补差分对接收的电流。 当输出信号已经建立时，电流 - 转向晶体管通过承载由互补差分对提供的电流的至少一部分来进行响应。 电流转向晶体管还驱动电流镜以将这些电流的其它部分转移到互补输出级。 相应地减少输出级中的存储电荷并提高其响应时间。 转换器速度进一步增强与电流转移晶体管相关联的元件，其防止电流镜和补偿输出级中的饱和。
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10.发明授权公开(公告)号：US08854096B1
公开(公告)日：2014-10-07
申请号：US14062368
申请日：2013-10-24
申请人： Michael R. Elliott , Brad P. Jeffries , Michael D. Keane , Johan H. Mansson , Axel Zafra Petersson
发明人： Michael R. Elliott , Brad P. Jeffries , Michael D. Keane , Johan H. Mansson , Axel Zafra Petersson
CPC分类号： H03K17/16 , H03L7/0812 , H03L7/097 , H04L25/0264
摘要： A transmission system may include an oscillator, a serializer, and a driver. The oscillator may generate at least two clock signals. The serializer may modulate a plurality of data streams based upon the at least two clock signals and a plurality of channels of data. The driver may receive and combine the plurality of data streams into a single output data stream, wherein the single output data stream has a clock frequency higher than frequency of each of the at least two clock signals.
摘要翻译： 传输系统可以包括振荡器，串行器和驱动器。 振荡器可以产生至少两个时钟信号。 串行器可以基于至少两个时钟信号和多个数据通道来调制多个数据流。 驱动器可以将多个数据流接收并组合成单个输出数据流，其中单个输出数据流的时钟频率高于至少两个时钟信号中的每一个的频率。
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