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    Buffer associated with multiple data communication channels
    4.
    发明授权
    Buffer associated with multiple data communication channels 有权
    与多个数据通信通道相关的缓冲区

    公开(公告)号：US06622186B1

    公开(公告)日：2003-09-16

    申请号：US09466508

    申请日：1999-12-17

    Applicant: Pascal Moniot ,  Marcello Coppola

    Inventor： Pascal Moniot ,  Marcello Coppola

    IPC: G06F1300

    CPC classification number: H04Q11/0478 ,  G06F12/023 ,  G06F12/0875 ,  H04L49/103

    Abstract: A buffer for adapting data flows from input channels to output channels is provided. The buffer includes a DRAM organized in blocks and a memory controller for managing assignment of the blocks to the chains of linked blocks. The DRAM contains, as a chain of linked blocks, data associated with each communication channel formed by a pair of input and output channels, and also contains a main queue of free blocks for listing unoccupied blocks. The memory controller includes a cache memory containing a partial queue of free blocks that the memory controller uses in managing block assignment. According to one embodiment, when a level of the partial queue reaches a predetermined minimum limit the cache memory is at least partially filled by a burst from the main queue, and when a level of the partial queue reaches a predetermined maximum limit the cache memory is at least partially emptied by a burst into the main queue. According to another embodiment, the partial queue stores a local image of a top portion of the main queue, and the memory controller exclusively uses the partial queue in assigning blocks to the chains of linked blocks. Further embodiments of the present invention provide methods of managing a buffer.

    Abstract translation: 提供了用于使数据流从输入通道适配到输出通道的缓冲器。 缓冲器包括以块为单位的DRAM，以及存储器控制器，用于管理块链接到链接块的链。 DRAM包含链接块链，与由一对输入和输出通道形成的每个通信通道相关联的数据，并且还包含用于列出未占用块的空闲块的主队列。 存储器控制器包括高速缓冲存储器，其包含存储器控制器在管理块分配中使用的空闲块的部分队列。 根据一个实施例，当部分队列的级别达到预定的最小限度时，高速缓冲存储器至少部分地由来自主队列的突发填充，并且当部分队列的级别达到预定的最大限制时，高速缓存存储器 至少部分地被突发排空到主队列中。 根据另一个实施例，部分队列存储主队列的顶部的本地图像，并且存储器控制器专门使用部分队列将块分配给链接块的链。 本发明的其他实施例提供了管理缓冲器的方法。

    Apparatus for postponing processing of interrupts by a microprocessor
    8.
    发明授权
    Apparatus for postponing processing of interrupts by a microprocessor 失效
    用于延迟由微处理器处理中断的装置

    公开(公告)号：US06192441B1

    公开(公告)日：2001-02-20

    申请号：US08690926

    申请日：1996-08-01

    Applicant: Claude Athenes ,  Pascal Moniot

    Inventor： Claude Athenes ,  Pascal Moniot

    IPC: G06F700

    CPC classification number: G06F13/24

    Abstract: This device controls the interrupts of a microprocessor based on events occurring in at least one entity associated with this microprocessor. The device organizes the storage of words representative of at least an origin and a type of the interrupt issued by the entity. The interrupts from the entity are stored in an area of a memory. When there is more than one entity, each entity has an area of memory allocated to it. The microprocessor can access these memory areas and process the interrupts. An indicator is also provided so that the device can tell when a memory area has become full.

    Abstract translation: 该设备基于与该微处理器相关联的至少一个实体中发生的事件来控制微处理器的中断。 该装置组织代表由该实体发出的至少一个起始点和一个中断类型的字的存储。 来自实体的中断存储在存储器的区域中。 当有多个实体时，每个实体都有一个内存分配区域。 微处理器可以访问这些存储区域并处理中断。 还提供了一个指示符，使得该设备可以告诉存储区何时已满。

    Method for associating a first address with a second address of reduced size for directly addressing a context memory on a computer
    10.
    发明授权
    Method for associating a first address with a second address of reduced size for directly addressing a context memory on a computer 有权
    用于将第一地址与缩小尺寸的第二地址相关联以便直接寻址计算机上的上下文存储器的方法

    公开(公告)号：US07275077B2

    公开(公告)日：2007-09-25

    申请号：US10395041

    申请日：2003-03-21

    Applicant: Pascal Moniot ,  David Furodet

    Inventor： Pascal Moniot ,  David Furodet

    IPC: G06F15/16 ,  G06F9/26 ,  H04L12/28

    CPC classification number: H04L61/6022 ,  H04L29/12009 ,  H04L29/12801 ,  H04L29/12839 ,  H04L61/6004

    Abstract: A method for associating with a first address a second address of reduced size, comprising: calculating a first intermediary address by the first address, the first intermediary address having a reduced size with respect to the first address; then choosing as a second address the first intermediary address if this second address is not associated with another first address, or, otherwise, calculating a second intermediary address by a first polynomial division of the first address, the second intermediary address having a reduced size as compared to the first address; then choosing as a second address the second intermediary address.

    Abstract translation: 一种用于将缩小尺寸的第二地址与第一地址相关联的方法，包括：通过所述第一地址计算第一中间地址，所述第一中间地址相对于所述第一地址具有减小的大小; 然后如果该第二地址不与另一个第一地址相关联，则选择第二地址作为第二中间地址，否则，通过第一地址的第一多项式除法来计算第二中间地址，第二中间地址的大小减小为 与第一个地址相比; 然后选择第二个地址作为第二个中间地址。

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