公开(公告)号：US20060132431A1

公开(公告)日：2006-06-22

申请号：US11015562

申请日：2004-12-17

申请人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

发明人： Oren Eliezer ,  Carl Panasik ,  John Wallberg ,  Robert Staszewski

IPC分类号： G09G5/00

CPC分类号： G06F3/0317 ,  G06F1/1616 ,  G06F1/1626 ,  G06F1/1684 ,  G06F1/1686 ,  G06F1/169 ,  G06F1/1694 ,  G06F1/1698 ,  G06F3/0354 ,  G06F3/03547 ,  G06F3/04886 ,  H04M2250/52 ,  H04W52/0267 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164 ,  Y02D70/23

摘要： System and method for interfacing with a digital computer using a multi-function device. A preferred embodiment comprises a multi-function device comprising a controller configured to process information and regulate operations of the multi-function device, a sensor coupled to the controller, the sensor configured to capture information in a movement of the multi-function device or a movement of an object applied to the multi-function device and to provide the information to the controller, wherein the information is used to determine movement information. The multi-function device further comprises a radio frequency circuit also coupled to the controller, the radio frequency circuit is configured to exchange information with other devices via a plurality of communications networks, wherein one of the other devices is a computer and the information shared is movement information from the multi-function device.

摘要翻译： 使用多功能设备与数字计算机进行接口的系统和方法。 优选实施例包括多功能设备，其包括被配置为处理信息并调节多功能设备的操作的控制器，耦合到控制器的传感器，被配置为捕获多功能设备的移动中的信息或 应用于多功能装置的物体的移动以及将信息提供给控制器，其中所述信息用于确定移动信息。 多功能设备还包括还耦合到控制器的射频电路，射频电路被配置为经由多个通信网络与其他设备交换信息，其中其他设备之一是计算机，并且共享的信息是 来自多功能设备的运动信息。

公开(公告)号：US20070103240A1

公开(公告)日：2007-05-10

申请号：US11619529

申请日：2007-01-03

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US20060038710A1

公开(公告)日：2006-02-23

申请号：US11203019

申请日：2005-08-11

申请人： Robert Staszewski ,  Oren Eliezer

发明人： Robert Staszewski ,  Oren Eliezer

IPC分类号： H03M3/00

CPC分类号： H03F3/24 ,  H03F2200/331 ,  H03M1/005 ,  H03M1/68 ,  H03M1/747 ,  H03M3/50 ,  H03M7/3022 ,  H04L27/361

摘要： A novel apparatus and method for a hybrid Cartesian/polar digital QAM modulator. The hybrid technique of the present invention utilizes a combination of an all digital phase locked loop (ADPLL) that features a wideband frequency modulation capability and a digitally controlled power amplifier (DPA) that features interpolation between 90 degree spaced quadrature phases. This structure is capable of performing either a polar operation or a Cartesian operation and can dynamically switch between them depending on the instantaneous value of a metric measured by a thresholder/router. In this manner, the disadvantages of each modulation technique are avoided while the benefits of each are exploited.

公开(公告)号：US20060119493A1

公开(公告)日：2006-06-08

申请号：US11297524

申请日：2005-12-07

申请人： Nir Tal ,  Sameh Rezeg ,  Robert Staszewski ,  Oren Eliezer ,  Ofer Friedman

发明人： Nir Tal ,  Sameh Rezeg ,  Robert Staszewski ,  Oren Eliezer ,  Ofer Friedman

IPC分类号： H03M3/00

CPC分类号： H03M7/3017 ,  H03M7/3022 ,  H03M7/3042

摘要： A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

摘要翻译： 一种采用具有噪声传递函数的Σ-Δ调制器的发射机，其适于在至少一个感兴趣的频带之外移位量化噪声。 提出了一种用于合成单环Σ-Δ调制器中的控制器的技术，使得噪声传递函数可以从满足某些条件的函数族中任意选择。 使用新颖的调制器设计技术，支持极坐标和笛卡尔（即正交）发射机结构。 呈现采用极性发射调制的发射机，其对数字控制的功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。 类似地，呈现采用笛卡尔发射调制的发射机，其对混合功率放大器的频谱发射进行整形，使得它们在一个或多个期望的频带中显着且充分衰减。

公开(公告)号：US20060291589A1

公开(公告)日：2006-12-28

申请号：US11203504

申请日：2005-08-11

申请人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

发明人： Oren Eliezer ,  Francis Cruise ,  Robert Staszewski ,  Jaimin Mehta

IPC分类号： H04L27/12

CPC分类号： H03F3/24 ,  H03C3/40 ,  H03C5/00 ,  H03F2200/324 ,  H03F2200/331 ,  H03F2200/336 ,  H04K1/02 ,  H04L27/04 ,  H04L27/2092 ,  H04L27/365

摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

摘要翻译： 一种用于复调制器的全数字正交架构的新型装置和方法。 复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。 调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号 。 相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。 提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

公开(公告)号：US20060033582A1

公开(公告)日：2006-02-16

申请号：US11149859

申请日：2005-06-10

申请人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

发明人： Robert Staszewski ,  Gennady Feygin ,  Oren Eliezer ,  Dirk Leipold

IPC分类号： H03L7/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L2207/50

摘要： A novel apparatus for and a method of estimating, calibrating and tracking in real-time the gain of a radio frequency (RF) digitally controlled oscillator (DCO) in an all-digital phase locked loop (ADPLL). Precise setting of the inverse DCO gain in the ADPLL modulating path allows direct wideband frequency modulation that is independent of the ADPLL loop bandwidth. The gain calibration technique is based on a steepest descent iterative algorithm wherein the phase ADPLL error is sampled and correlated with the modulating data to generate a gradient. The gradient is then scaled and added to the current value of the DCO gain multiplier.

摘要翻译： 一种用于实时估计，校准和跟踪全数字锁相环（ADPLL）中的射频（RF）数字控制振荡器（DCO）的增益的新型装置和方法。 ADPLL调制路径中逆DCO增益的精确设置允许直接宽带频率调制，与ADPLL环路带宽无关。 增益校准技术基于最速下降迭代算法，其中相位ADPLL误差被采样并与调制数据相关以产生梯度。 然后将梯度缩放并添加到DCO增益乘数的当前值。

公开(公告)号：US20070085623A1

公开(公告)日：2007-04-19

申请号：US11550957

申请日：2006-10-19

申请人： Robert Staszewski ,  John Wallberg

发明人： Robert Staszewski ,  John Wallberg

IPC分类号： H03L5/00

CPC分类号： H03L7/0991 ,  H03L7/085 ,  H03L7/1806 ,  H03L2207/50 ,  H04L27/361 ,  H04L27/368

摘要： A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

摘要翻译： 一种用于在基于全数字锁相环（ADPLL）的数字控制振荡器（DCO）中增益归一化的新颖机制，其可操作地在调制路径和PLL环路之间分离增益归一化乘法功能。 调制环路（称为调制路径乘法器）的增益归一化包括全位分辨率高精度乘法函数。 另一方面，PLL环路的增益归一化具有显着更低的分辨率，因此需要较低复杂度的乘法器逻辑电路。

公开(公告)号：US20070182496A1

公开(公告)日：2007-08-09

申请号：US11551124

申请日：2006-10-19

申请人： John Wallberg ,  Robert Staszewski ,  Vanessa Bodrero

发明人： John Wallberg ,  Robert Staszewski ,  Vanessa Bodrero

IPC分类号： H03B5/12

CPC分类号： G01R31/31727 ,  H03B2201/0283 ,  H03J2200/10

摘要： A novel testing mechanism operative to test large capacitor arrays such as those used in a digitally controlled crystal oscillator (DCXO). The invention is adapted for use in DCXO circuits that employ dynamic element matching in their array decoding circuits. The invention combines the use of DEM during regular operation of the DCXO with a testing technique that greatly reduces the number of tests required. The invention tests the capacitors in the array on a row by row, wherein all the capacitors in a row are tested lumped together and treated as a single entity, which results in significantly reduced testing time. This permits the measurement of significantly higher frequency deviations due to the larger capacitances associated with an entire row of capacitors being tested

摘要翻译： 一种新颖的测试机制，用于测试诸如数字控制晶体振荡器（DCXO）中使用的大电容阵列。 本发明适用于在其阵列解码电路中采用动态元件匹配的DCXO电路中。 本发明结合了DCXO正常运行期间DEM的使用与大大减少所需测试次数的测试技术。 本发明逐行测试阵列中的电容器，其中一行中的所有电容器被集中测试并被处理为单个实体，这导致测试时间显着减少。 这允许由于与被测试的整个电容器相关联的较大电容而测量显着更高的频率偏差

公开(公告)号：US20060103566A1

公开(公告)日：2006-05-18

申请号：US11274965

申请日：2005-11-15

申请人： Sudheer Vemulapalli ,  John Wallberg ,  Prasant Vallur ,  Robert Staszewski

发明人： Sudheer Vemulapalli ,  John Wallberg ,  Prasant Vallur ,  Robert Staszewski

IPC分类号： H03M1/12

CPC分类号： H04L27/361 ,  G04F10/005 ,  H03L7/091

摘要： A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.

摘要翻译： 一种新颖的时间数字转换器（TDC），用作数字无线电处理器内的全数字PLL中的相位/频率检测器和电荷泵替换。 TDC内核基于伪差分数字架构，使其对NMOS和PMOS晶体管不匹配不敏感。 时间转换分辨率等于CMOS的逆变器传播延迟，例如20 ps，这是CMOS中最优的逻辑电平再生定时。 TDC自校准，估计精度优于1％。 TDC电路还可以用作大型SoC模具中模拟电路的CMOS工艺强度估计器。 该电路还采用电源管理电路，将功耗降至非常低的水平。

公开(公告)号：US20070085621A1

公开(公告)日：2007-04-19

申请号：US11551103

申请日：2006-10-19

申请人： Robert Staszewski ,  John Wallberg

发明人： Robert Staszewski ,  John Wallberg

IPC分类号： H03B5/12

CPC分类号： H03C3/095 ,  H03C3/0975 ,  H03L7/08 ,  H03L2207/50

摘要： A novel apparatus for and method of acquisition and tracking bank cooperation in a digitally controlled oscillator (DCO) within an all digital phase locked loop (ADPLL). The acquisition bits of the acquisition bank are used as an extension of the modulation range. The PLL and TX tuning data are broken up (i.e. apportioned) into acquisition components and tracking components. This permits the use of two different capacitor banks (i.e. the tracking and acquisition banks) for modulation rather than just a single capacitor bank as in the prior art schemes. Incorporating the tracking and acquisition bit varactors, the cooperation scheme of the present invention permits the re-centering of the tracking bank to handle natural frequency drift of the DCO and the widening of the modulation range.

摘要翻译： 一种用于在全数字锁相环（ADPLL）内的数字控制振荡器（DCO）中采集和跟踪存储体协作的新型装置和方法。 采集库的采集位用作调制范围的扩展。 PLL和TX调谐数据被分解（即分配）到采集组件和跟踪组件中。 这允许如现有技术方案那样使用两个不同的电容器组（即，跟踪和采集组）用于调制，而不仅仅是单个电容器组。 结合跟踪和采集位变容二极管，本发明的协作方案允许跟踪组重新对中以处理DCO的固有频率漂移和调制范围的扩大。