公开(公告)号：US08569842B2

公开(公告)日：2013-10-29

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L27/088 ,  H01L27/098 ,  H01L29/161 ,  H01L29/20 ,  H01L29/778 ,  H01L29/788

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08970262B2

公开(公告)日：2015-03-03

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H03B1/00 ,  H03K3/00 ,  H01L27/088 ,  H03K17/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/098 ,  H01L29/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20140062544A1

公开(公告)日：2014-03-06

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20120175635A1

公开(公告)日：2012-07-12

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L29/788 ,  H01L29/20 ,  H01L29/161 ,  H01L27/088 ,  H01L27/098

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20130193525A1

公开(公告)日：2013-08-01

申请号：US13362038

申请日：2012-01-31

申请人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

发明人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

IPC分类号： H01L27/06

CPC分类号： H01L27/0207 ,  H01L21/84 ,  H01L21/845 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/78 ,  H03K17/063 ,  H03K17/102

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

公开(公告)号：US08866253B2

公开(公告)日：2014-10-21

申请号：US13362038

申请日：2012-01-31

申请人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

发明人： Rolf Weis ,  Gerald Deboy ,  Michael Treu ,  Armin Willmeroth ,  Hans Weber

IPC分类号： H01L27/00

CPC分类号： H01L27/0207 ,  H01L21/84 ,  H01L21/845 ,  H01L27/06 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/78 ,  H03K17/063 ,  H03K17/102

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二半导体器件，每个第二半导体器件具有在第一和第二负载端子与控制端子之间的负载路径。 第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。 每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子，并且其中一个第二半导体器件的控制端子连接到第一半导体器件的负载端子之一。 每个第二半导体器件具有至少一个器件特性。 第二半导体器件中的至少一个的至少一个器件特征与第二半导体器件中的其它器件的相应器件特性不同。

公开(公告)号：US08971080B2

公开(公告)日：2015-03-03

申请号：US13546510

申请日：2012-07-11

申请人： Rolf Weis ,  Gerald Deboy

发明人： Rolf Weis ,  Gerald Deboy

IPC分类号： H02M7/217

CPC分类号： H02M3/33592 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  Y02B70/1475

摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径 第一负载端子和第二负载端子和控制端子。 第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。 具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。 每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。 第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

公开(公告)号：US20140016386A1

公开(公告)日：2014-01-16

申请号：US13546510

申请日：2012-07-11

申请人： Rolf Weis ,  Gerald Deboy

发明人： Rolf Weis ,  Gerald Deboy

IPC分类号： H02M7/00 ,  H02M7/217 ,  H02M7/06

CPC分类号： H02M3/33592 ,  H02M3/1588 ,  H02M7/217 ,  Y02B70/1466 ,  Y02B70/1475

摘要： A circuit arrangement includes a rectifier circuit having a first and a second load terminal, a first semiconductor device having a load path and a control terminal and a plurality of n, with n>1, second semiconductor devices, each having a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. The series circuit with the first semiconductor device and the second semiconductor devices are connected between the load terminals of the rectifier circuit. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 一种电路装置包括具有第一和第二负载端子的整流电路，具有负载路径的第一半导体器件和具有n≥1的多个n，第二半导体器件具有负载路径 第一负载端子和第二负载端子和控制端子。 第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。 具有第一半导体器件和第二半导体器件的串联电路连接在整流器电路的负载端子之间。 每个第二半导体器件的控制端子连接到其它第二半导体器件之一的负载端子。 第二半导体器件中的一个具有连接到第一半导体器件的负载端子之一的控制端子。

公开(公告)号：US09035690B2

公开(公告)日：2015-05-19

申请号：US13599946

申请日：2012-08-30

申请人： Rolf Weis

发明人： Rolf Weis

IPC分类号： H03K17/567 ,  H03K17/10 ,  H03K17/687

CPC分类号： H03K5/08 ,  H03K17/102 ,  H03K17/567 ,  H03K17/687 ,  H03K2017/6875

摘要： A circuit arrangement includes a first semiconductor device having a load path and a number of second semiconductor devices. Each second semiconductor device has a control terminal and a load path between a first load terminal and a second load terminal. The second semiconductor devices have their load paths connected in series and connected in series with the load path of the first semiconductor device. Each of the second semiconductor devices has a load terminal of one of the first semiconductor device and of one of the second semiconductor devices associated thereto and a voltage limiting element coupled between the control terminal of one of the second semiconductor devices and the load terminal associated with that one of the second semiconductor devices.

摘要翻译： 电路装置包括具有负载路径和多个第二半导体器件的第一半导体器件。 每个第二半导体器件具有在第一负载端子和第二负载端子之间的控制端子和负载路径。 第二半导体器件的负载路径串联连接并与第一半导体器件的负载路径串联连接。 每个第二半导体器件具有第一半导体器件中的一个和与其相关联的第二半导体器件中的一个的负载端子，以及耦合在第二半导体器件中的一个的控制端子与与之相关联的负载端子之间的电压限制元件 那个第二个半导体器件之一。

公开(公告)号：US07829879B2

公开(公告)日：2010-11-09

申请号：US12033519

申请日：2008-02-19

申请人： Rolf Weis ,  Thomas Happ

发明人： Rolf Weis ,  Thomas Happ

IPC分类号： H01L29/02

CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： An integrated circuit includes a first contact, a second contact, and a U-shaped access device coupled to the first contact and the second contact. The integrated circuit includes self-aligned dielectric material isolating the first contact from the second contact.

摘要翻译： 集成电路包括耦合到第一触点和第二触点的第一触点，第二触点和U形存取装置。 集成电路包括将第一接触与第二接触隔离的自对准电介质材料。