公开(公告)号：US20120305993A1

公开(公告)日：2012-12-06

申请号：US13484490

申请日：2012-05-31

申请人： Armin Willmeroth ,  Franz Hirler ,  Hans Weber ,  Michael Treu

发明人： Armin Willmeroth ,  Franz Hirler ,  Hans Weber ,  Michael Treu

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/7803 ,  H01L29/7831

摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.

摘要翻译： 半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。 所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接 的MOSFET器件在负载端子之间。 所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到 晶体管器件的至少一个控制端子。

公开(公告)号：US20110089481A1

公开(公告)日：2011-04-21

申请号：US12976107

申请日：2010-12-22

申请人： Armin Willmeroth ,  Michael Treu

发明人： Armin Willmeroth ,  Michael Treu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

摘要： A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.

摘要翻译： 描述了具有增加的栅 - 漏电容的MOS晶体管。 一个实施例提供了第一导电类型的漂移区。 至少一个晶体管单元具有体区，通过体区与漂移区分离的源极区以及邻近体区设置并通过栅介质与体区介电绝缘的栅电极。 在漂移区域中布置有至少一个第一导电类型的补偿区域。 至少一个反馈电极被布置在与身体区隔一定距离处，该区域通过反馈电介质与漂移区介电绝缘，并且与电极导电连接。

公开(公告)号：US20100264467A1

公开(公告)日：2010-10-21

申请号：US12426008

申请日：2009-04-17

申请人： Dethard Peters ,  Peter Friedrichs ,  Rudolf Elpelt ,  Larissa Wehrhahn-Kilian ,  Michael Treu ,  Roland Rupp

发明人： Dethard Peters ,  Peter Friedrichs ,  Rudolf Elpelt ,  Larissa Wehrhahn-Kilian ,  Michael Treu ,  Roland Rupp

IPC分类号： H01L29/812

CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/8122

摘要： A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential. The at least one control zone and the at least one shielding zone have different geometries or different orientations in a plain that is perpendicular to a current flow direction of the component.

摘要翻译： 具有屏蔽结构的晶体管组件。 一个实施例提供了源极端子，漏极端子和控制端子。 第一导电类型的源极区域连接到源极端子。 第一导电类型的漏极区域连接到漏极端子。 漂移区设置在源区和排水区之间。 提供了结点控制结构，用于控制在漏区和源区之间的漂移区中的接合区，至少包括一个控制区。 屏蔽结构布置在结点控制结构和漏区之间的漂移区中，并且至少包括与第一导电类型互补的第二导电类型的屏蔽区。 屏蔽区域与屏蔽电位端子相连。 所述至少一个控制区域和所述至少一个屏蔽区域在垂直于所述部件的当前流动方向的平原中具有不同的几何形状或不同取向。

公开(公告)号：US20080017947A1

公开(公告)日：2008-01-24

申请号：US11780265

申请日：2007-07-19

申请人： Michael Treu

发明人： Michael Treu

IPC分类号： H01L27/095 ,  H01L29/00

CPC分类号： H01L29/872 ,  H01L24/05 ,  H01L29/0603 ,  H01L29/0615 ,  H01L29/1608 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2924/0002 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05552

摘要： A circuit having a Schottky contact component is disclosed. One embodiment provides a semiconductor substrate having a layer of a first conductivity type, a metal layer, and delimited semiconductor regions of a second conductivity type opposite the first conductivity type, provided in or on the main surface, in order to increase the resistance of the Schottky contact component to overcurrents. At least the predominant number of delimited semiconductor regions of the second conductivity type being provided in the form of islands with a predetermined distance greater than a minimum interaction distance required for interaction of the islands to achieve an associated shielding effect.

摘要翻译： 公开了具有肖特基接触部件的电路。 一个实施例提供一种半导体衬底，其具有第一导电类型的层，金属层和设置在主表面中或主表面上的与第一导电类型相反的第二导电类型的界定的半导体区域，以便增加 肖特基接触元件过电流。 至少第二导电类型的界定半导体区域的主要数量以岛的形式提供，其具有大于岛的相互作用所需的最小相互作用距离的预定距离，以实现相关联的屏蔽效应。

公开(公告)号：US08803205B2

公开(公告)日：2014-08-12

申请号：US13484490

申请日：2012-05-31

申请人： Armin Willmeroth ,  Franz Hirler ,  Hans Weber ,  Michael Treu

发明人： Armin Willmeroth ,  Franz Hirler ,  Hans Weber ,  Michael Treu

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L27/088 ,  H01L27/098 ,  H01L29/0634 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/7803 ,  H01L29/7831

摘要： A semiconductor device includes a gate terminal, at least one control terminal and first and second load terminals and at least one device cell. The at least one device cell includes a MOSFET device having a load path and a control terminal, the control terminal coupled to the gate terminal and a JFET device having a load path and a control terminal, the load path connected in series with the load path of the MOSFET device between the load terminals. The at least one device cell further includes a first coupling transistor having a load path and a control terminal, the load path coupled between the control terminal of the JFET device and one of the source terminal and the gate terminal, and the control terminal coupled to the at least one control terminal of the transistor device.

摘要翻译： 半导体器件包括栅极端子，至少一个控制端子以及第一和第二负载端子以及至少一个器件单元。 所述至少一个器件单元包括具有负载路径和控制端子的MOSFET器件，所述控制端子耦合到所述栅极端子以及具有负载路径和控制端子的JFET器件，所述负载路径与所述负载路径串联连接 的MOSFET器件在负载端子之间。 所述至少一个器件单元还包括具有负载路径和控制端子的第一耦合晶体管，所述负载路径耦合在所述JFET器件的控制端子与所述源极端子和所述栅极端子之一之间，并且所述控制端子耦合到 晶体管器件的至少一个控制端子。

公开(公告)号：US08525254B2

公开(公告)日：2013-09-03

申请号：US12854974

申请日：2010-08-12

申请人： Michael Treu ,  Ralf Siemieniec

发明人： Michael Treu ,  Ralf Siemieniec

IPC分类号： H01L29/24 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A semiconductor device as described herein includes a silicon carbide semiconductor body. A trench extends into the silicon carbide semiconductor body at a first surface. A gate dielectric and a gate electrode are formed within the trench. A body zone of a first conductivity type adjoins to a sidewall of the trench, the body zone being electrically coupled to a contact via a body contact zone including a higher maximum concentration of dopants than the body zone. An extension zone of the first conductivity type is electrically coupled to the contact via the body zone, wherein a maximum concentration of dopants of the extension zone along a vertical direction perpendicular to the first surface is higher than the maximum concentration of dopants of the body zone along the vertical direction. A distance between the first surface and a bottom side of the extension zone is larger than the distance between the first surface and the bottom side of the trench.

摘要翻译： 如本文所述的半导体器件包括碳化硅半导体本体。 沟槽在第一表面延伸到碳化硅半导体本体中。 栅极电介质和栅电极形成在沟槽内。 第一导电类型的身体区域与沟槽的侧壁相邻，身体区域通过身体接触区域电耦合到接触区，该身体接触区域包括比身体区域更高的掺杂剂浓度。 第一导电类型的延伸区域经由体区电耦合到接触，其中延伸区域沿垂直于第一表面的垂直方向的掺杂剂的最大浓度高于体区的掺杂剂的最大浓度 沿垂直方向。 延伸区域的第一表面和底侧之间的距离大于沟槽的第一表面和底侧之间的距离。

公开(公告)号：US08450196B2

公开(公告)日：2013-05-28

申请号：US11924093

申请日：2007-10-25

申请人： Roland Rupp ,  Thomas Gutt ,  Michael Treu

发明人： Roland Rupp ,  Thomas Gutt ,  Michael Treu

IPC分类号： H01L21/28

CPC分类号： H01L21/0495 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0485 ,  H01L21/268 ,  H01L21/2683 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/872

摘要： Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

摘要翻译： 公开了一种包括SiC上电接触的集成电路的生产。 一个实施例提供在SiC衬底上制造电接触，其中通过在SiC衬底上照射和吸收激光脉冲在SiC衬底的边界表面上产生导电接触。

公开(公告)号：US08102012B2

公开(公告)日：2012-01-24

申请号：US12426008

申请日：2009-04-17

申请人： Dethard Peters ,  Peter Friedrichs ,  Rudolf Elpelt ,  Larissa Wehrhahn-Kilian ,  Michael Treu ,  Roland Rupp

发明人： Dethard Peters ,  Peter Friedrichs ,  Rudolf Elpelt ,  Larissa Wehrhahn-Kilian ,  Michael Treu ,  Roland Rupp

IPC分类号： H01L27/088

CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/8122

摘要： A transistor component having a shielding structure. One embodiment provides a source terminal, a drain terminal and control terminal. A source zone of a first conductivity type is connected to the source terminal. A drain zone of the first conductivity type is connected to the drain terminal. A drift zone is arranged between the source zone and the drain zone. A junction control structure is provided for controlling a junction zone in the drift zone between the drain zone and the source zone, at least including one control zone. A shielding structure is arranged in the drift zone between the junction control structure and the drain zone and at least includes a shielding zone of a second conductivity type being complementarily to the first conductivity type. The shielding zone is connected to a terminal for a shielding potential. The at least one control zone and the at least one shielding zone have different geometries or different orientations in a plain that is perpendicular to a current flow direction of the component.

摘要翻译： 具有屏蔽结构的晶体管组件。 一个实施例提供了源极端子，漏极端子和控制端子。 第一导电类型的源极区域连接到源极端子。 第一导电类型的漏极区域连接到漏极端子。 漂移区设置在源区和排水区之间。 提供了结点控制结构，用于控制在漏区和源区之间的漂移区中的接合区，至少包括一个控制区。 屏蔽结构布置在结点控制结构和漏区之间的漂移区中，并且至少包括与第一导电类型互补的第二导电类型的屏蔽区。 屏蔽区域与屏蔽电位端子相连。 所述至少一个控制区域和所述至少一个屏蔽区域在垂直于所述部件的当前流动方向的平原中具有不同的几何形状或不同取向。

公开(公告)号：US07763506B2

公开(公告)日：2010-07-27

申请号：US11852853

申请日：2007-09-10

申请人： Michael Treu ,  Roland Rupp ,  Heinz Mitlehner ,  Rudolf Elpelt ,  Peter Friedrichs ,  Larissa Wehrhahn-Kilian

发明人： Michael Treu ,  Roland Rupp ,  Heinz Mitlehner ,  Rudolf Elpelt ,  Peter Friedrichs ,  Larissa Wehrhahn-Kilian

IPC分类号： H01L21/337

CPC分类号： H01L29/8083 ,  H01L29/0692 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66909

摘要： A method for making an integrated circuit including vertical junction field effect transistors is disclosed. One embodiment creates a vertical junction field effect transistor using a fault-tolerant or alignment-tolerant production process. The device performance is not harmed, even if misalignments in consecutive semiconductor processing steps occur.

摘要翻译： 公开了一种制造包括垂直结型场效应晶体管的集成电路的方法。 一个实施例使用容错或对准容限的制造工艺创建垂直结型场效应晶体管。 即使在连续的半导体处理步骤中发生未对准，器件性能也不会受到损害。

公开(公告)号：US20080258183A1

公开(公告)日：2008-10-23

申请号：US11789045

申请日：2007-04-23

申请人： Roland Rupp ,  Stefan Woehlert ,  Thomas Gutt ,  Michael Treu

发明人： Roland Rupp ,  Stefan Woehlert ,  Thomas Gutt ,  Michael Treu

IPC分类号： H01L29/80 ,  H01L27/095

CPC分类号： H01L29/47 ,  H01L21/0485 ,  H01L21/0495 ,  H01L21/268 ,  H01L21/32134 ,  H01L23/528 ,  H01L29/1608 ,  H01L29/417 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66901 ,  H01L29/66909 ,  H01L29/808 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device.

摘要翻译： 一种制造器件的方法包括将一个或多个金属化层沉积到衬底上，局部加热所述一个或多个金属化层的区域以获得衬底/金属化层化合物或金属化层化合物，所述化合物包括蚀刻 - 选择性不同于区域外的一个或多个金属化层的蚀刻介质的选择性，以及根据该区域或区域外的蚀刻选择性，去除该区域或区域外的一个或多个金属化层， 通过用蚀刻介质蚀刻以形成该器件。