公开(公告)号：US08569842B2

公开(公告)日：2013-10-29

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L27/088 ,  H01L27/098 ,  H01L29/161 ,  H01L29/20 ,  H01L29/778 ,  H01L29/788

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US08970262B2

公开(公告)日：2015-03-03

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H03B1/00 ,  H03K3/00 ,  H01L27/088 ,  H03K17/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423 ,  H01L27/098 ,  H01L29/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20140062544A1

公开(公告)日：2014-03-06

申请号：US13978373

申请日：2012-01-09

申请人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

发明人： Rolf Weis ,  Franz Hirler ,  Martin Feldtkeller ,  Gerald Deboy ,  Matthias Stecher ,  Armin Willmeroth

IPC分类号： H01L27/088 ,  H03K17/06

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 公开了一种包括具有负载路径的第一半导体器件和多个第二晶体管的半导体器件布置，每个第二晶体管具有在第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接，每个第二晶体管的控制端连接到其它第二晶体管之一的负载端，第二晶体管中的一个 晶体管的控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20120175635A1

公开(公告)日：2012-07-12

申请号：US13275151

申请日：2011-10-17

申请人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

发明人： Rolf Weis ,  Franz Hirler ,  Matthias Stecher ,  Armin Willmeroth ,  Gerald Deboy ,  Martin Feldtkeller

IPC分类号： H01L27/06 ,  H01L29/778 ,  H01L29/788 ,  H01L29/20 ,  H01L29/161 ,  H01L27/088 ,  H01L27/098

CPC分类号： H01L27/0207 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/088 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/098 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7835 ,  H01L29/7838 ,  H03K17/06

摘要： A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

摘要翻译： 半导体器件布置包括具有负载路径的第一半导体器件和多个第二晶体管，每个具有第一和第二负载端子与控制端子之间的负载路径。 第二晶体管的负载路径串联连接并与第一晶体管的负载路径串联连接。 每个第二晶体管的控制端连接到其它第二晶体管的负载端子。 第二晶体管中的一个具有其控制端子连接到第一半导体器件的负载端子之一。

公开(公告)号：US20090224302A1

公开(公告)日：2009-09-10

申请号：US12043429

申请日：2008-03-06

申请人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

发明人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L27/0733 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.

摘要翻译： 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外，半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接，或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层，介电层位于其之间，并形成至少一个附加电容器。

公开(公告)号：US20060006386A1

公开(公告)日：2006-01-12

申请号：US10926581

申请日：2004-08-25

申请人： Franz Hirler ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Gerald Deboy ,  Ralf Henninger

发明人： Franz Hirler ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Uwe Wahl ,  Gerald Deboy ,  Ralf Henninger

IPC分类号： H01L29/04

CPC分类号： H01L29/407 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body between a first and a second doped terminal zone. At least one field electrode is provided, which is arranged in the drift zone, extends into the drift zone proceeding from the first side and is configured in a manner electrically insulated from the semiconductor body.

摘要翻译： 描述半导体部件。 在一个实施例中，半导体部件包括具有第一侧和第二侧的半导体本体。 提供了漂移区，其布置在第一侧下方的半导体本体中，并且在第一和第二掺杂末端区之间沿半导体本体的第一横向方向延伸。 设置至少一个场电极，其布置在漂移区中，从第一侧延伸到漂移区，并且以与半导体本体电绝缘的方式配置。

公开(公告)号：US07973359B2

公开(公告)日：2011-07-05

申请号：US12194384

申请日：2008-08-19

申请人： Franz Hirler ,  Armin Willmeroth ,  Anton Mauder ,  Gerald Deboy ,  Holger Kapels ,  Carolin Tolksdorf ,  Frank Pfirsch

发明人： Franz Hirler ,  Armin Willmeroth ,  Anton Mauder ,  Gerald Deboy ,  Holger Kapels ,  Carolin Tolksdorf ,  Frank Pfirsch

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7811 ,  H01L2224/02166 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled to at least one of the near-surface bond contact areas.

摘要翻译： 具有电荷载体补偿结构的半导体器件。 在一个实施例中，半导体器件具有具有栅极和源极结构的中心电池区。 至少一个键合接触区域电耦合到栅极结构或源极结构。 电容增大场板电耦合到近表面接合区域中的至少一个。

公开(公告)号：US20100044788A1

公开(公告)日：2010-02-25

申请号：US12194384

申请日：2008-08-19

申请人： Franz Hirler ,  Armin Willmeroth ,  Anton Mauder ,  Gerald Deboy ,  Holger Kapels ,  Carolin Tolksdorf ,  Frank Pfirsch

发明人： Franz Hirler ,  Armin Willmeroth ,  Anton Mauder ,  Gerald Deboy ,  Holger Kapels ,  Carolin Tolksdorf ,  Frank Pfirsch

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L24/05 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/7811 ,  H01L2224/02166 ,  H01L2924/181 ,  H01L2924/00

摘要： A semiconductor device with a charge carrier compensation structure. In one embodiment, the semiconductor device has a central cell field with a gate and source structure. At least one bond contact area is electrically coupled to the gate structure or the source structure. A capacitance-increasing field plate is electrically coupled to at least one of the near-surface bond contact areas.

摘要翻译： 具有电荷载体补偿结构的半导体器件。 在一个实施例中，半导体器件具有具有栅极和源极结构的中心电池区。 至少一个键合接触区域电耦合到栅极结构或源极结构。 电容增大场板电耦合到近表面接合区域中的至少一个。

公开(公告)号：US07977737B2

公开(公告)日：2011-07-12

申请号：US12043429

申请日：2008-03-06

申请人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

发明人： Armin Willmeroth ,  Winfried Kaindl ,  Carolin Tolksdorf ,  Anton Mauder ,  Holger Kapels ,  Gerald Deboy ,  Franz Hirler

IPC分类号： H01L29/66 ,  H01L21/337

CPC分类号： H01L27/0733 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device with inherent capacitances and method for its production. The semiconductor device has an inherent feedback capacitance between a control electrode and a first electrode. In addition, the semiconductor device has an inherent drain-source capacitance between the first electrode and a second electrode. At least one monolithically integrated additional capacitance is connected in parallel to the inherent feedback capacitance or in parallel to the inherent drain-source capacitance. The additional capacitance comprises a first capacitor surface and a second capacitor surface opposite the first capacitor surface. The capacitor surfaces are structured conductive layers of the semiconductor device on a front side of the semiconductor body, between which a dielectric layer is located and which form at least one additional capacitor.

摘要翻译： 具有固有电容的半导体器件及其制造方法。 半导体器件在控制电极和第一电极之间具有固有的反馈电容。 此外，半导体器件在第一电极和第二电极之间具有固有的漏极 - 源极电容。 至少一个单片集成附加电容与固有反馈电容并联连接，或与固有漏 - 源电容并联连接。 附加电容包括与第一电容器表面相对的第一电容器表面和第二电容器表面。 电容器表面是半导体器件的前侧上的半导体器件的结构化导电层，介电层位于其之间，并形成至少一个附加电容器。

公开(公告)号：US07777278B2

公开(公告)日：2010-08-17

申请号：US12020197

申请日：2008-01-25

申请人： Franz Hirler ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Gerald Deboy ,  Ralf Henninger ,  Uwe Wahl

发明人： Franz Hirler ,  Armin Willmeroth ,  Markus Schmitt ,  Carolin Tolksdorf ,  Gerald Deboy ,  Ralf Henninger ,  Uwe Wahl

IPC分类号： H01L21/336

CPC分类号： H01L29/407 ,  H01L29/0847 ,  H01L29/0852 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7825 ,  H01L29/8611 ,  H01L29/872

摘要： A semiconductor component is described. In one embodiment, the semiconductor component includes a semiconductor body with a first side and a second side. A drift zone is provided, which is arranged in the semiconductor body below the first side and extends in a first lateral direction of the semiconductor body between a first and a second doped terminal zone. At least one field electrode is provided, which is arranged in the drift zone, extends into the drift zone proceeding from the first side and is configured in a manner electrically insulated from the semiconductor body.

摘要翻译： 描述半导体部件。 在一个实施例中，半导体部件包括具有第一侧和第二侧的半导体本体。 提供了漂移区，其布置在第一侧下方的半导体本体中，并且在第一和第二掺杂末端区之间沿半导体本体的第一横向方向延伸。 设置至少一个场电极，其布置在漂移区中，从第一侧延伸到漂移区，并且以与半导体本体电绝缘的方式配置。