公开(公告)号：US20080217721A1

公开(公告)日：2008-09-11

申请号：US11684261

申请日：2007-03-09

申请人： Roman J. Hamerski ,  Zerui Chen ,  James Man-Fai Hong ,  Johnny Duc Van Chiem ,  Christopher D. Hruska ,  Timothy Eastman

发明人： Roman J. Hamerski ,  Zerui Chen ,  James Man-Fai Hong ,  Johnny Duc Van Chiem ,  Christopher D. Hruska ,  Timothy Eastman

IPC分类号： H01L31/00 ,  H01L21/425

CPC分类号： H01L29/365 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/861 ,  H01L29/8618 ,  H01L29/868 ,  H01L29/88

摘要： A high-efficiency power semiconductor rectifier device (10) comprising a δP++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the δP++ layer (12) of supersaturated P-doped silicon.

摘要翻译： 一种高效率功率半导体整流器件（10），包括δP++层（12），P体（14），N漂移区（16），N +衬底（18），阳极（20）和 阴极（22）。 制造器件（10）的方法包括以下步骤：在N +衬底（18）上沉积N漂移区（16），将硼注入N漂移区（16）以产生P体区（14） ），在P体区域（14）上形成硅化钛层（56），并将一部分注入的硼在硅化钛层（56）和P体区域（14）之间的界面区域集中 ）以产生过饱和P掺杂硅的δP++层（12）。

公开(公告)号：US07847315B2

公开(公告)日：2010-12-07

申请号：US11684261

申请日：2007-03-09

申请人： Roman J. Hamerski ,  Zerui Chen ,  James Man-Fai Hong ,  Johnny Duc Van Chiem ,  Christopher D. Hruska ,  Timothy Eastman

发明人： Roman J. Hamerski ,  Zerui Chen ,  James Man-Fai Hong ,  Johnny Duc Van Chiem ,  Christopher D. Hruska ,  Timothy Eastman

IPC分类号： H01L29/36 ,  H01L29/86

CPC分类号： H01L29/365 ,  H01L29/0619 ,  H01L29/66136 ,  H01L29/66151 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/861 ,  H01L29/8618 ,  H01L29/868 ,  H01L29/88

摘要： A high-efficiency power semiconductor rectifier device (10) comprising a δP++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the δP++ layer (12) of supersaturated P-doped silicon.

摘要翻译： 一种高效率功率半导体整流器件（10），包括δP++层（12），P体（14），N漂移区（16），N +衬底（18），阳极（20）和 阴极（22）。 制造器件（10）的方法包括以下步骤：在N +衬底（18）上沉积N漂移区（16），将硼注入N漂移区（16）以产生P体区（14） ），在P体区域（14）上形成硅化钛层（56），并将一部分注入的硼在硅化钛层（56）和P体区域（14）之间的界面区域集中 ）以产生过饱和P掺杂硅的δP++层（12）。

公开(公告)号：US06717229B2

公开(公告)日：2004-04-06

申请号：US10096203

申请日：2002-03-11

申请人： Walter R. Buchanan ,  Roman J. Hamerski ,  Wayne A. Smith

发明人： Walter R. Buchanan ,  Roman J. Hamerski ,  Wayne A. Smith

IPC分类号： H01L27095

CPC分类号： H01L29/0619 ,  H01L29/872

摘要： A diode (20), having first and second conductive layers (24,26), a conductive pad (28), and a distributed reverse surge guard (22), provides increased protection from reverse current surges. The surge guard (22) includes an outer loop (42) of P+-type surge guard material and an inner grid (44) of linear sections (46, 48) which form a plurality of inner loops extending inside the outer loop (42). The surge guard (22) distributes any reverse current over the area of the conductive pad (28) to provide increased protection from transient threats such as electrostatic discharge (ESD) and during electrical testing.

摘要翻译： 具有第一和第二导电层（24,26），导电焊盘（28）和分布式反向浪涌保护器（22）的二极管（20）提供增强的防止反向电流浪涌的保护。 浪涌保护器（22）包括P +型防浪涌保护材料的外环（42）和线性部分（46,48）的内格栅（44），其形成在外环内延伸的多个内环 （42）。 浪涌保护器（22）在导电焊盘（28）的区域上分布任何反向电流，以提供对诸如静电放电（ESD）和电测试之类的瞬态威胁的更大保护。

公开(公告)号：US06462393B2

公开(公告)日：2002-10-08

申请号：US09812738

申请日：2001-03-20

申请人： Walter R. Buchanan ,  Roman J. Hamerski

发明人： Walter R. Buchanan ,  Roman J. Hamerski

IPC分类号： H01L27095

CPC分类号： H01L29/872 ,  H01L29/0619

摘要： An improved Schottky device, having a low resistivity layer of semiconductor material, a high resistivity layer of semiconductor material and a buried dopant region positioned in the high resistivity layer utilized to reduce reverse leakage current. The low resistivity layer can be an N+ material while the high resistivity layer can be an N− layer. The buried dopant region can be of P+ material, thus forming a PN junction with an associated charge depletion zone in the N− layer and an associated low reverse leakage current. The location of the P+ material allows for a full Schottky barrier between the N− material and a barrier metal to be maintained, thus the device experiences a low forward voltage drop.

摘要翻译： 一种改进的肖特基器件，具有半导体材料的低电阻率层，半导体材料的高电阻率层和位于高电阻率层中的掩埋掺杂剂区域，用于减少反向泄漏电流。 低电阻率层可以是N +材料，而高电阻率层可以是N层。 埋入的掺杂区可以是P +材料，从而形成具有N层中相关联的电荷耗尽区的PN结和相关联的低反向漏电流。 P +材料的位置允许保持N材料和阻挡金属之间的全肖特基势垒，因此器件经历低的正向压降。

公开(公告)号：US06500741B2

公开(公告)日：2002-12-31

申请号：US10109503

申请日：2002-03-28

申请人： Walter R. Buchanan ,  Roman J. Hamerski

发明人： Walter R. Buchanan ,  Roman J. Hamerski

IPC分类号： H01L2122

CPC分类号： H01L29/66136

摘要： An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined pattern of dopant material. Once heated, the remaining top layer of dopant material is removed and the resultant substrate and diffused epitaxial layer is divided so as to form a plurality of separate electrical devices. Each patch of dopant material corresponds to the middle portion of an individual electrical device devisable from the resultant substrate and defused based and the diffusion region achieved by the heating process will be deepest substantially towards the middle portion of each respective electrical device and will be comparatively shallower at the edges of each such electrical device.

公开(公告)号：US06376346B1

公开(公告)日：2002-04-23

申请号：US09670232

申请日：2000-09-28

申请人： Walter R. Buchanan ,  Roman J. Hamerski

发明人： Walter R. Buchanan ,  Roman J. Hamerski

IPC分类号： H01L2122

CPC分类号： H01L29/66136

摘要： An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined pattern of dopant material. Once heated, the remaining top layer of dopant material is removed and the resultant substrate and diffused epitaxial layer is divided so as to form a plurality of separate electrical devices. Each patch of dopant material corresponds to the middle portion of an individual electrical device devisable from the resultant substrate and defused based and the diffusion region achieved by the heating process will be deepest substantially towards the middle portion of each respective electrical device and will be comparatively shallower at the edges of each such electrical device.

摘要翻译： 一种诸如可用于高电压应用中的二极管的电气装置，其中电气装置由产生多个高压电气装置的方法制造，本方法包括提供具有预定衬底导电类型的半导体材料的衬底， 衬底通常由单晶生长方法形成，形成与衬底的上表面邻接的第二外延层，外延层具有预定的第二层导电型，然后在预定的图案上形成顶层掺杂剂材料 第二外延层的上表面。 掺杂剂材料的这种预定图案通常采用可通过掩模和蚀刻工艺或通过丝网印刷工艺实现的贴片阵列的形式。 一旦在外延层的上表面上形成或以其它方式沉积预定图案的掺杂剂材料，则衬底，外延层和顶层被加热以在外延层中形成扩散区，该扩散区与预定的 掺杂剂材料的图案。 一旦被加热，去除剩余的顶层掺杂剂材料，并将得到的衬底和扩散的外延层分开以形成多个单独的电子器件。 掺杂剂材料的每个贴片对应于从所得衬底设计的单个电气装置的中间部分，并且基于所述衬底进行基于消融，并且通过加热过程实现的扩散区域将基本上朝向每个相应电气装置的中间部分最深，并且将相对较浅 在每个这样的电气设备的边缘。

公开(公告)号：US06362112B1

公开(公告)日：2002-03-26

申请号：US09708779

申请日：2000-11-08

申请人： Roman J. Hamerski

发明人： Roman J. Hamerski

IPC分类号： H01L21302

CPC分类号： H01L21/3083

摘要： A single step etched moat (24), having a regular grid work mask (28) of mesa shields (42) and edge termination shields (44), is utilized to form, in a single etching step, semiconductor devices (22) having lengthy edge terminations for reduced edge termination failure. The desired semiconductor devices (22) include a high resistivity, monocrystalline grown substrate layer (30), a low resistivity epitaxial base layer (32), and a low resistivity top layer (36). The regular grid work of mesa shields (42) and edge termination shields (44) define open grid lines (48) and open grid rings (46). The open grid lines (48) are wider than the open grid rings (46), so that as the moats (24) are etched, a deeper grid line divot (50) is formed below the open grid lines (48) and a more shallow grid ring divot is formed below the open grid ring (46).

摘要翻译： 在单个蚀刻步骤中，利用具有台面屏蔽（42）和边缘终止屏蔽（44）的规则格栅工作掩模（28）的单步刻蚀护城河（24），以形成具有冗长长度的半导体器件 用于边缘终止故障的边缘终端。 期望的半导体器件（22）包括高电阻率单晶生长衬底层（30），低电阻率外延基底层（32）和低电阻率顶层（36）。 台面屏蔽（42）和边缘终端屏蔽（44）的规则网格工作定义了开放的网格线（48）和开放的网格环（46）。 开放的栅格线（48）比开放的栅格环（46）宽，使得随着护城河（24）被蚀刻，在开放栅格线（48）的下方形成更深的栅格线纹（50） 在开放格栅环（46）的下面形成浅网格环纹。

公开(公告)号：US06791161B2

公开(公告)日：2004-09-14

申请号：US10118729

申请日：2002-04-08

申请人： Roman J. Hamerski

发明人： Roman J. Hamerski

IPC分类号： H01L29861

CPC分类号： H01L29/66106 ,  H01L29/866

摘要： The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device. An additional device can optionally be produced in which a low contact resistance layer is implanted into an exterior surface of the junction layer.

摘要翻译： 本发明涉及一种新颖的半导体器件，其可以有效地制造用于齐纳二极管应用中。 提供了精密齐纳二极管及其制造方法。 本发明的齐纳二极管由具有范围或电阻率的半导体衬底层制成，在其上生长外延层。 外延层的电阻率大于衬底的电阻率。 二极管还具有与衬底相同导电类型的掺杂半导体材料的内部区域。 内部区域延伸穿过外延层并进入基底层。 二极管还具有不同于衬底的导电类型的结层。 接合层形成在外延表面中，并且接合层与内部区域形成内部P / N结，并与器件的外围部分形成外围P / N结。 可以可选地制造附加装置，其中将低接触电阻层注入到结层的外表面中。

公开(公告)号：US06479885B2

公开(公告)日：2002-11-12

申请号：US10108826

申请日：2002-03-28

申请人： Walter R. Buchanan ,  Roman J. Hamerski

发明人： Walter R. Buchanan ,  Roman J. Hamerski

IPC分类号： H01L31036

CPC分类号： H01L29/66136

摘要： An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process. Once the predetermined pattern of dopant material is formed or otherwise deposited upon the upper surface of the epitaxial layer, the substrate, epitaxial and top layers are heated to form a diffusion region in the epitaxial layer, this diffusion region having a specific correlation to the predetermined pattern of dopant material. Once heated, the remaining top layer of dopant material is removed and the resultant substrate and diffused epitaxial layer is divided so as to form a plurality of separate electrical devices. Each patch of dopant material corresponds to the middle portion of an individual electrical device devisable from the resultant substrate and defused based and the diffusion region achieved by the heating process will be deepest substantially towards the middle portion of each respective electrical device and will be comparatively shallower at the edges of each such electrical device.

摘要翻译： 一种诸如可用于高电压应用中的二极管的电气装置，其中电气装置由产生多个高压电气装置的方法制造，本方法包括提供具有预定衬底导电类型的半导体材料的衬底， 衬底通常由单晶生长方法形成，形成与衬底的上表面邻接的第二外延层，外延层具有预定的第二层导电型，然后以预定图案形成掺杂剂的顶层材料 第二外延层的上表面。 掺杂剂材料的这种预定图案通常采用可通过掩模和蚀刻工艺或通过丝网印刷工艺实现的贴片阵列的形式。 一旦在外延层的上表面上形成或以其它方式沉积预定图案的掺杂剂材料，则衬底，外延层和顶层被加热以在外延层中形成扩散区，该扩散区与预定的 掺杂剂材料的图案。 一旦被加热，去除剩余的顶层掺杂剂材料，并将得到的衬底和扩散的外延层分开以形成多个单独的电子器件。 掺杂剂材料的每个贴片对应于从所得衬底设计的单个电气装置的中间部分，并且基于所述衬底进行基于消融，并且通过加热过程实现的扩散区域将基本上朝向每个相应电气装置的中间部分最深，并且将相对较浅 在每个这样的电气设备的边缘。

公开(公告)号：US06803298B2

公开(公告)日：2004-10-12

申请号：US10455119

申请日：2003-06-04

申请人： Roman J. Hamerski ,  Gary W. Gladish

发明人： Roman J. Hamerski ,  Gary W. Gladish

IPC分类号： H01L2122

CPC分类号： H01L29/66136 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/861 ,  Y10S257/927

摘要： A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystalline growth forms the substrate layer (22), and this high quality crystal is used as the high resistivity layer in the device (20). The base layer (24) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface (32) of the substrate layer (22) at a fast rate greater than approximately 2 microns/minute. The top layer (26) is a diffusion layer diffused into an upper surface (34) of the substrate layer (22). To control stress in the wafer (28), the epitaxial base is doped with germanium.

摘要翻译： 具有基底层（22），基底层（24）和顶层（26）的高压电气装置（20）提供超过1000V的高电压特性。 从通过单晶生长形成的锭（30）切片晶片（28）形成基板层（22），该高质量晶体用作器件（20）中的高电阻率层。 基极层（24）是以大于约2微米/分钟的快速速率沉积在衬底层（22）的下表面（32）上的高度掺杂的低电阻率外延层。 顶层（26）是扩散到衬底层（22）的上表面（34）中的扩散层。 为了控制晶片（28）中的应力，外延基底掺杂有锗。