公开(公告)号：US20120199808A1

公开(公告)日：2012-08-09

申请号：US13381633

申请日：2011-04-01

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Al ,  Jiewen Fan

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Al ,  Jiewen Fan

IPC分类号： H01L29/775 ,  B82Y99/00

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention provides a high voltage-resistant lateral double-diffused transistor based on a nanowire device, which relates to the field of microelectronics semiconductor devices. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s). The invention can improve the high voltage-resistant capability of a lateral double-diffused transistor based on a silicon nanowire MOS transistor.

摘要翻译： 本发明提供了一种基于纳米线器件的高耐压横向双扩散晶体管，其涉及微电子半导体器件的领域。 横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向 圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和 漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且 相对介电常数为1-4的绝缘材料填充在S形结构内。 本发明可以提高基于硅纳米线MOS晶体管的横向双扩散晶体管的耐高压能力。

公开(公告)号：US08564031B2

公开(公告)日：2013-10-22

申请号：US13381633

申请日：2011-04-01

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Ai ,  Jiewen Fan

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Gengyu Yang ,  Yujie Ai ,  Jiewen Fan

IPC分类号： H01L29/76

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775

摘要： The invention provides a high voltage-resistant lateral double-diffused transistor. The lateral double-diffused MOS transistor includes a channel region, a gate dielectric, a gate region, a source region, a drain region, a source end extension region and a drain end S-shaped drifting region, wherein the channel region has a lateral cylindrical silicon nanowire structure, on which a layer of gate dielectric is uniformly covered, the gate region is on the gate dielectric, the gate region and the gate dielectric completely surround the channel region, the source end extension region lies between the source region and the channel region, the drain end S-shaped drifting region lies between the drain region and the channel region, the plan view of the drain end S-shaped drifting region is in the form of single or multiple S-shaped structure(s), and an insulating material with a relative dielectric constant of 1-4 is filled within the S-shaped structure(s).

摘要翻译： 本发明提供了一种耐高压横向双扩散晶体管。 横向双扩散MOS晶体管包括沟道区，栅极电介质，栅极区，源极区，漏极区，源极延伸区和漏极端S形漂移区，其中沟道区具有侧向 圆柱形硅纳米线结构，其上均匀地覆盖一层栅极电介质，栅极区在栅极电介质上，栅极区和栅极电介质完全围绕沟道区，源极延伸区位于源区和 漏极端S形漂移区域位于漏极区域和沟道区域之间，排水端S形漂移区域的平面图为单个或多个S形结构的形式，并且 相对介电常数为1-4的绝缘材料填充在S形结构内。

公开(公告)号：US08592276B2

公开(公告)日：2013-11-26

申请号：US13501711

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US20130214810A1

公开(公告)日：2013-08-22

申请号：US13879967

申请日：2012-02-28

申请人： Ru Huang ,  Jibin Zou ,  Changze Liu ,  Runsheng Wang ,  Jiewen Fan ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Changze Liu ,  Runsheng Wang ,  Jiewen Fan ,  Yangyuan Wang

IPC分类号： G01R31/26

CPC分类号： G01R31/2642 ,  G01R31/2621 ,  H01L22/14 ,  H01L22/34

摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.

摘要翻译： 提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。 测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。 本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。 在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。 在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合 用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

公开(公告)号：US20130011980A1

公开(公告)日：2013-01-10

申请号：US13501711

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.

摘要翻译： 本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。 与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力 ，并减少泄漏电流和漏极引起的屏障降低（DIBL）。 另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

公开(公告)号：US20120302027A1

公开(公告)日：2012-11-29

申请号：US13511123

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  B82Y40/00

CPC分类号： H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

摘要翻译： 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US08866507B2

公开(公告)日：2014-10-21

申请号：US13382415

申请日：2011-09-29

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

IPC分类号： G01R31/02 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14 ,  G01R31/2621 ,  G01R31/2642 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for testing trap density in a gate dielectric layer of a semiconductor device having no substrate contact is provided in the invention. A source and a drain of the device are bilateral symmetric, and probes and cables of a test instrument connecting to the source and the drain are bilateral symmetric. Firstly, bias settings at the gate, the source and the drain are controlled so that the device is under an initial state that an inversion layer is not formed and traps in the gate dielectric layer impose no confining effects on charges. After that, the following steps are repeated sequentially to form a loop by changing the bias settings: 1) carriers flow into the channel through the source and the drain to form an inversion layer, and a portion of carriers are confined by the traps in the gate dielectric layer; 2) carriers of the inversion layer flow back to the source and the drain respectively, whereas the carriers confined by the traps in the gate dielectric layer do not flow back to the channel; 3) carriers confined by the traps in the gate dielectric layer flow out through the drain terminal only; and the trap density of the gate dielectric layer are calculated according to the period of the loop, the size of the channel of the device, and DC currents at the source and the drain. The method is simple and effective and is easy to setup the instruments with a low cost. The method is applicable to be used in testing traps in the gate dielectric layer of the devices that have no substrate contact, especially the surrounding-gate device.

摘要翻译： 本发明提供了一种在没有衬底接触的半导体器件的栅介质层中测试阱密度的方法。 器件的源极和漏极是双向对称的，连接到源极和漏极的测试仪器的探头和电缆是双边对称的。 首先，控制栅极，源极和漏极处的偏置设置，使得器件处于不形成反型层的初始状态，并且栅极电介质层中的陷阱对电荷没有施加约束效应。 之后，顺序重复以下步骤，通过改变偏置设置来形成一个环路：1）载流子通过源极和漏极流入沟道，形成一个反型层，一部分载流子被陷阱限制在 栅介质层; 2）反转层的载流子分别流回到源极和漏极，而由栅极电介质层中的陷阱限制的载流子不流回到沟道; 3）由栅极电介质层中的陷阱限制的载流子仅通过漏极端子流出; 并且根据环路的周期，器件的通道的尺寸以及源极和漏极处的直流电流来计算栅极介电层的陷阱密度。 该方法简单有效，易于以低成本设置仪器。 该方法适用于在不与衬底接触的器件的栅极电介质层中测试陷阱，特别是周围栅极器件。

公开(公告)号：US20130075701A1

公开(公告)日：2013-03-28

申请号：US13503240

申请日：2011-11-18

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

IPC分类号： H01L29/66

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

摘要翻译： 本发明公开了一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制造方法。 阵列包括纳米线器件，纳米线器件连接区域和栅极连接区域，其中纳米线器件具有圆筒形状，并且包括硅纳米线通道，栅极介电层和栅极区域，纳米线通道被包围 通过所述栅极介电层，并且所述栅极介电层被所述栅极区域包围; 纳米线器件以六边形形式布置以形成编程单元，纳米线器件连接区域是三个纳米线器件的连接节点并且固定到硅支撑体。 本发明可以实现互连的复杂控制逻辑，并且适用于具有高集成度和高​​速度的数字/模拟和混合信号电路。

公开(公告)号：US09099500B2

公开(公告)日：2015-08-04

申请号：US13503240

申请日：2011-11-18

申请人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

发明人： Ru Huang ,  Jibin Zou ,  Runsheng Wang ,  Jiewen Fan ,  Changze Liu ,  Yangyuan Wang

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/02 ,  B82Y99/00

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/02603 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

摘要： The present invention discloses a hexagonal programmable array based on a silicon nanowire field effect transistor and a method for fabricating the same. The array includes a nanowire device, a nanowire device connection region and a gate connection region, wherein, the nanowire device has a cylinder shape, and includes a silicon nanowire channel, a gate dielectric layer, and a gate region, the nanowire channel being surrounded by the gate dielectric layer, and the gate dielectric layer being surrounded by the gate region; the nanowire devices are arranged in a hexagon shape to form programming unit, the nanowire device connection region is a connection node of three nanowire devices and secured to a silicon supporter. The present invention can achieve a complex control logic of interconnections and is suitable for a digital/analog and a mixed-signal circuit having a high integration degree and a high speed.

摘要翻译： 本发明公开了一种基于硅纳米线场效应晶体管的六边形可编程阵列及其制造方法。 阵列包括纳米线器件，纳米线器件连接区域和栅极连接区域，其中纳米线器件具有圆筒形状，并且包括硅纳米线通道，栅极介电层和栅极区域，纳米线通道被包围 通过所述栅极介电层，并且所述栅极介电层被所述栅极区域包围; 纳米线器件以六边形形式布置以形成编程单元，纳米线器件连接区域是三个纳米线器件的连接节点并且固定到硅支撑体。 本发明可以实现互连的复杂控制逻辑，并且适用于具有高集成度和高​​速度的数字/模拟和混合信号电路。

公开(公告)号：US09034702B2

公开(公告)日：2015-05-19

申请号：US13511123

申请日：2011-11-18

申请人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

发明人： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC分类号： H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

摘要： Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

摘要翻译： 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。