公开(公告)号：US20140035010A1

公开(公告)日：2014-02-06

申请号：US13562659

申请日：2012-07-31

申请人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。 临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。 该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下 定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。 集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

公开(公告)号：US08580634B1

公开(公告)日：2013-11-12

申请号：US13609941

申请日：2012-09-11

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/42392

摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.

摘要翻译： 在一个示例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成图案化的硬掩模，其中图案化的硬掩模具有开口 其暴露所述翅片的一部分，通过所述翅片的暴露部分上的所述图案化硬掩模中的开口进行翅片回流处理，以限定具有不同于所述第一横截面构造的横截面构造的纳米线结构， 以及形成至少部分地围绕纳米线结构延伸的栅极结构。

公开(公告)号：US08748309B2

公开(公告)日：2014-06-10

申请号：US13618035

申请日：2012-09-14

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/44

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

摘要翻译： 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。 第一区域由第一材料形成，第二区域由第二材料形成。 在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。 被照射的层被蚀刻以形成凹部。

公开(公告)号：US08735272B2

公开(公告)日：2014-05-27

申请号：US13562659

申请日：2012-07-31

申请人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。 临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。 该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下 定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。 集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

公开(公告)号：US20140077274A1

公开(公告)日：2014-03-20

申请号：US13618035

申请日：2012-09-14

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

摘要翻译： 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。 第一区域由第一材料形成，第二区域由第二材料形成。 在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。 被照射的层被蚀刻以形成凹部。

公开(公告)号：US08691696B2

公开(公告)日：2014-04-08

申请号：US13476860

申请日：2012-05-21

申请人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John Iacoponi

发明人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John Iacoponi

IPC分类号： H01L21/311

CPC分类号： H01L21/311 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76831 ,  H01L29/66545

摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.

摘要翻译： 为形成集成电路提供了方法。 在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。 侧壁间隔件形成在牺牲心轴的相邻侧壁处。 侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。 侧壁间隔物还具有与基底基板间隔开的上部。 上部具有倾斜的外表面。 第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。 在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。 凹槽的重新设计简洁直观。

公开(公告)号：US20140070285A1

公开(公告)日：2014-03-13

申请号：US13611652

申请日：2012-09-12

申请人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

发明人： Ruilong Xie ,  Ponoth Shom ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Robert J. Miller

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636

摘要： One method includes forming a sacrificial gate structure above a substrate, forming a first sidewall spacer adjacent a sacrificial gate electrode, removing a portion of the first sidewall spacer to expose a portion of the sidewalls of the sacrificial gate electrode, and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode and above a residual portion of the first sidewall spacer. The method further includes forming a first layer of insulating material above the liner layer, forming a second sidewall spacer above the first layer of insulating material and adjacent the liner layer, performing an etching process to remove the second sidewall spacer and sacrificial gate cap layer to expose an upper surface of the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity at least partially defined laterally by the liner layer, and forming a replacement gate structure in the cavity.

摘要翻译： 一种方法包括在衬底上形成牺牲栅极结构，形成邻近牺牲栅电极的第一侧壁间隔物，去除第一侧壁间隔物的一部分以暴露牺牲栅电极的侧壁的一部分，以及在衬底上形成衬层 牺牲栅电极的暴露的侧壁和第一侧壁间隔物的残留部分之上。 该方法还包括在衬垫层之上形成绝缘材料的第一层，在第一绝缘材料层之上形成第二侧壁隔离层并与衬里层相邻，执行蚀刻工艺以除去第二侧壁间隔物和牺牲栅极盖层， 暴露牺牲栅电极的上表面，去除牺牲栅电极以限定通过衬层至少部分地限定的侧壁的栅极腔，以及在空腔中形成替换栅极结构。

公开(公告)号：US09117877B2

公开(公告)日：2015-08-25

申请号：US13350908

申请日：2012-01-16

申请人： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

发明人： Xiuyu Cai ,  Ruilong Xie ,  Jin Cho ,  John Iacoponi

IPC分类号： H01L21/311 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66795

摘要： Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

摘要翻译： 本文公开了在FinFET和其它半导体器件上形成隔离结构的各种方法，以及具有这种隔离结构的所得器件。 在一个示例中，该方法包括在半导体衬底中形成多个间隔开的沟槽，其中沟槽限定用于FinFET器件的鳍片，在沟槽中形成绝缘材料层，其中绝缘材料层覆盖下部 翅片的一部分而不是翅片的上部，在翅片的上部形成保护材料，并且在氧化环境中进行加热处理，以在翅片的被覆盖的下部形成热氧化物区域。

公开(公告)号：US08551843B1

公开(公告)日：2013-10-08

申请号：US13465486

申请日：2012-05-07

申请人： Xiuyu Cai ,  Ruilong Xie

发明人： Xiuyu Cai ,  Ruilong Xie

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

摘要： One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.

摘要翻译： 本文公开的一种方法包括形成第一，第二和第三栅极堆叠，其中栅极堆叠中的一个是位于隔离结构上方的隔离堆叠，并且每个栅极堆叠由位于栅极层上方的三层硬掩模材料构成 电极材料。 该方法还涉及在第一和隔离栅极堆叠被掩蔽的同时形成靠近第二栅极堆叠的侧壁间隔物，在第二和隔离栅极叠层被掩蔽的同时形成靠近第一栅极堆叠的侧壁间隔，在多个栅极之间形成抛光停止层 堆叠，在蚀刻停止层上执行另一蚀刻工艺，间隔物材料层，以及位于隔离栅极堆叠上方或附近的第二层硬掩模材料，并执行化学机械抛光工艺，以去除位于 抛光止蚀层。

公开(公告)号：US20130309868A1

公开(公告)日：2013-11-21

申请号：US13476860

申请日：2012-05-21

申请人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

发明人： Xiuyu Cai ,  Xunyuan Zhang ,  Ruilong Xie ,  Errol T. Ryan ,  John A. Iacoponi

IPC分类号： H01L21/311

CPC分类号： H01L21/311 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76831 ,  H01L29/66545

摘要： Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.

摘要翻译： 为形成集成电路提供了方法。 在一个实施例中，该方法包括形成覆盖在基底衬底上的牺牲心轴。 侧壁间隔件形成在牺牲心轴的相邻侧壁处。 侧壁间隔件具有靠近基底基底的下部，并且下部具有相对于基底的基本垂直的外表面。 侧壁间隔物还具有与基底基板间隔开的上部。 上部具有倾斜的外表面。 第一电介质层形成在基底衬底上，并且与侧壁间隔物的上部的至少一部分共形。 在形成第一介电层之后去除侧壁间隔物的上部，以在第一介电层中形成具有凹入轮廓的凹部。 凹槽的重新设计简洁直观。