公开(公告)号：US20140035010A1

公开(公告)日：2014-02-06

申请号：US13562659

申请日：2012-07-31

申请人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/772 ,  H01L21/283

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。 临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。 该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下 定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。 集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

公开(公告)号：US08524592B1

公开(公告)日：2013-09-03

申请号：US13584055

申请日：2012-08-13

申请人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

摘要翻译： 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

公开(公告)号：US08580634B1

公开(公告)日：2013-11-12

申请号：US13609941

申请日：2012-09-11

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/42392

摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a patterned hard mask above the fin, wherein the patterned hard mask has an opening that exposes a portion of the fin, performing a fin reflow process through the opening in the patterned hard mask on the exposed portion of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration, and forming a gate structure that extends at least partially around the nanowire structure.

摘要翻译： 在一个示例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成图案化的硬掩模，其中图案化的硬掩模具有开口 其暴露所述翅片的一部分，通过所述翅片的暴露部分上的所述图案化硬掩模中的开口进行翅片回流处理，以限定具有不同于所述第一横截面构造的横截面构造的纳米线结构， 以及形成至少部分地围绕纳米线结构延伸的栅极结构。

公开(公告)号：US08748309B2

公开(公告)日：2014-06-10

申请号：US13618035

申请日：2012-09-14

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/44

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

摘要翻译： 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。 第一区域由第一材料形成，第二区域由第二材料形成。 在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。 被照射的层被蚀刻以形成凹部。

公开(公告)号：US08735272B2

公开(公告)日：2014-05-27

申请号：US13562659

申请日：2012-07-31

申请人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method for fabricating an integrated circuit includes forming a temporary gate structure on a semiconductor substrate. The temporary gate structure includes a temporary gate material disposed between two spacer structures. The method further includes forming a first directional silicon nitride liner overlying the temporary gate structure and the semiconductor substrate, etching the first directional silicon nitride liner overlying the temporary gate structure and the temporary gate material to form a trench between the spacer structures, while leaving the directional silicon nitride liner overlying the semiconductor substrate in place, and forming a replacement metal gate structure in the trench. An integrated circuit includes a replacement metal gate structure overlying a semiconductor substrate, a silicide region overlying the semiconductor substrate and positioned adjacent the replacement gate structure; a directional silicon nitride liner overlying a portion of the replacement gate structure; and a contact plug in electrical communication with the silicide region.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成临时栅极结构。 临时栅极结构包括设置在两个间隔结构之间的临时栅极材料。 该方法还包括形成覆盖临时栅极结构和半导体衬底的第一定向硅氮化物衬垫，蚀刻覆盖临时栅极结构的第一定向氮化硅衬底和临时栅极材料，以在间隔物结构之间形成沟槽，同时留下 定向氮化硅衬垫覆盖半导体衬底就位，并在沟槽中形成置换金属栅极结构。 集成电路包括覆盖半导体衬底的替代金属栅极结构，覆盖半导体衬底并邻近置换栅结构定位的硅化物区; 覆盖所述替代栅极结构的一部分的定向氮化硅衬垫; 以及与硅化物区域电连通的接触插塞。

公开(公告)号：US20140077274A1

公开(公告)日：2014-03-20

申请号：US13618035

申请日：2012-09-14

申请人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/4958 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/4966 ,  H01L29/66545

摘要： Integrated circuits with improved gate uniformity and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure including a first region and a second region and a structure surface formed by the first region and the second region. The first region is formed by a first material and the second region is formed by a second material. In the method, the structure surface is exposed to a gas cluster ion beam (GCIB) and an irradiated layer is formed in the structure in both the first region and the second region. The irradiated layer is etched to form a recess.

摘要翻译： 提供了具有改善的栅极均匀性的集成电路以及用于制造这种集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供包括第一区域和第二区域以及由第一区域和第二区域形成的结构表面的结构。 第一区域由第一材料形成，第二区域由第二材料形成。 在该方法中，将结构表面暴露于气体簇离子束（GCIB），在第一区域和第二区域的结构中形成照射层。 被照射的层被蚀刻以形成凹部。

公开(公告)号：US08541274B1

公开(公告)日：2013-09-24

申请号：US13609828

申请日：2012-09-11

申请人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

发明人： Ruilong Xie ,  Xiuyu Cai, Jr. ,  Kangguo Cheng ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

摘要： In one example, the method disclosed herein includes forming a fin comprised of a semiconducting material, wherein the fin has a first, as-formed cross-sectional configuration, forming a sacrificial gate structure above the fin, forming sidewall spacers adjacent at least a portion of the sacrificial gate structure and removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin. The method also includes the steps of performing a fin reflow process on the exposed portions of the fin to define a nanowire structure having a cross-sectional configuration that is different from the first cross-sectional configuration and forming a replacement gate structure in the gate cavity and at least partially around the nanowire structure.

摘要翻译： 在一个实例中，本文公开的方法包括形成由半导体材料构成的鳍片，其中鳍片具有第一成形截面构造，在鳍片之上形成牺牲栅极结构，形成邻近至少一部分的侧壁间隔物 的牺牲栅极结构，并且去除牺牲栅极结构，从而限定暴露鳍片的一部分的栅极腔。 该方法还包括以下步骤：在鳍的暴露部分上执行翅片回流处理以限定具有与第一截面构造不同的横截面构造的纳米线结构，并在栅腔中形成替代栅极结构 并且至少部分地围绕纳米线结构。

公开(公告)号：US09190471B2

公开(公告)日：2015-11-17

申请号：US13446350

申请日：2012-04-13

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/84

CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/84 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/78

摘要： A semiconductor structure including a semiconductor wafer. The semiconductor wafer includes a gate structure, a first trench in the semiconductor wafer adjacent to a first side of the gate structure and a second trench adjacent to a second side of the gate structure, the first and second trenches filled with a doped epitaxial silicon to form a source in the filled first trench and a drain in the filled second trench such that each of the source and drain are recessed and have an inverted facet. In a preferred exemplary embodiment, the epitaxial silicon is doped with boron.

摘要翻译： 包括半导体晶片的半导体结构。 所述半导体晶片包括栅极结构，所述半导体晶片中与所述栅极结构的第一侧相邻的第一沟槽和与所述栅极结构的第二侧相邻的第二沟槽，所述第一和第二沟槽填充有掺杂的外延硅， 在填充的第一沟槽中形成源极，并且在填充的第二沟槽中形成漏极，使得源极和漏极中的每一个凹入并具有倒置的面。 在优选的示例性实施例中，外延硅掺杂有硼。

公开(公告)号：US09054211B2

公开(公告)日：2015-06-09

申请号：US13540801

申请日：2012-07-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。