公开(公告)号：US08234596B2

公开(公告)日：2012-07-31

申请号：US12552010

申请日：2009-09-01

申请人： Ryuji Ogawa ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

发明人： Ryuji Ogawa ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

摘要翻译： 根据本发明的实施例的图形数据创建方法包括：使用通过应用过程模拟获得的第一结果来提取边缘误差模式以基于评估目标单元图案来屏蔽图案数据，将过程模拟应用于基于 通过将周边环境图案布置在边缘误差图案中，使得通过创建掩模图案数据获得的第二结果和对掩模图案数据应用处理模拟而得到的第一结果比第一结果更差，从而产生具有周边环境图案的评估对象单元图案， 以及当存在致命错误时，基于评估对象单元图案来校正评估对象单元格图案或掩模图案数据。

公开(公告)号：US20100081294A1

公开(公告)日：2010-04-01

申请号：US12552010

申请日：2009-09-01

申请人： Ryuji OGAWA ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

发明人： Ryuji OGAWA ,  Masahiro Miyairi ,  Shimon Maeda ,  Suigen Kyoh ,  Satoshi Tanaka

IPC分类号： H01L21/027 ,  G06F17/50

CPC分类号： G03F1/36

摘要： A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.

摘要翻译： 根据本发明的实施例的图形数据创建方法包括：使用通过应用过程模拟获得的第一结果来提取边缘误差模式以基于评估目标单元图案来屏蔽图案数据，将过程模拟应用于基于 通过将周边环境图案布置在边缘误差图案中，使得通过创建掩模图案数据获得的第二结果和对掩模图案数据应用处理模拟而得到的第一结果比第一结果更差，从而产生具有周边环境图案的评估对象单元图案， 以及当存在致命错误时，基于评估对象单元图案来校正评估对象单元格图案或掩模图案数据。

公开(公告)号：US20100067777A1

公开(公告)日：2010-03-18

申请号：US12536900

申请日：2009-08-06

申请人： Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

发明人： Katsuyoshi Kodera ,  Satoshi Tanaka ,  Shimon Maeda ,  Suigen Kyoh ,  Soichi Inoue ,  Ryuji Ogawa

IPC分类号： G06K9/00

CPC分类号： G03F1/44 ,  G03F1/36

摘要： An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.

摘要翻译： 1.一种评价图案生成方法，包括将评价对象图案的周边区域划分为多个网格; 当将掩模函数值赋予预定网格时，通过光刻处理将评估对象图案转印到晶片上时，计算电路图案的图像强度; 计算网格的掩码函数值，使得影响评估对象图案对晶片的转印性能的光学图像特征量被设置为图像强度的图像强度的成本函数满足预定参考，当 评估目标模式的光刻性能评估; 以及生成与所述掩模功能值对应的评估图案。

公开(公告)号：US07194704B2

公开(公告)日：2007-03-20

申请号：US11012491

申请日：2004-12-16

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455

CPC分类号： G06F17/5081 ,  H01L21/0271

摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

摘要翻译： 公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分 在维修准则上。

公开(公告)号：US20050204322A1

公开(公告)日：2005-09-15

申请号：US11012491

申请日：2004-12-16

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Suigen Kyoh ,  Kyoko Izuha ,  Ryuji Ogawa ,  Satoshi Tanaka ,  Soichi Inoue ,  Hirotaka Ichikawa

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/027 ,  H01L21/82

CPC分类号： G06F17/5081 ,  H01L21/0271

摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.

摘要翻译： 公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点 相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分 在维修准则上。

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

申请人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

发明人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

摘要翻译： 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US20110041104A1

公开(公告)日：2011-02-17

申请号：US12805093

申请日：2010-07-12

申请人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5036

摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

摘要翻译： 半导体电路图案设计方法包括以下操作。 通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。 创建基于设计模式的掩模图案数据。 预测通过掩模图案数据在衬底上形成的预测图案。 检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。 将差值与预定的允许变化量进行比较。 如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

公开(公告)号：US07784020B2

公开(公告)日：2010-08-24

申请号：US11429077

申请日：2006-05-08

申请人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5036

摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

摘要翻译： 半导体电路图案设计方法包括以下操作。 通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。 创建基于设计模式的掩模图案数据。 预测通过掩模图案数据在衬底上形成的预测图案。 检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。 将差值与预定的允许变化量进行比较。 如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

公开(公告)号：US20060271907A1

公开(公告)日：2006-11-30

申请号：US11429077

申请日：2006-05-08

申请人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Fumihiro Minami ,  Toshiaki Ueda ,  Ryuji Ogawa ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5031 ,  G06F17/5036

摘要： A semiconductor circuit pattern design method includes the following operations. A design pattern is created by placing a plurality of cells in each functional block as a unit of the semiconductor circuit and executing routing among the plurality of placed cells. Mask pattern data based on the design pattern is created. A predictive pattern to be formed on the substrate by the mask pattern data is predicted. A difference amount between the predictive pattern and a target pattern to be formed on the substrate by the mask pattern data is checked. The difference amount is compared with a predetermined allowable variation amount. If the difference amount is larger than the allowable variation amount in the comparison, at least one of placement and routing of the cells in the design pattern corresponding to the mask pattern data used to predict the predictive pattern is corrected.

摘要翻译： 半导体电路图案设计方法包括以下操作。 通过将每个功能块中的多个单元放置为半导体电路的单元并在多个放置的单元之间执行布线来创建设计图案。 创建基于设计模式的掩模图案数据。 预测通过掩模图案数据在衬底上形成的预测图案。 检查通过掩模图案数据在衬底上形成的预测图案和目标图案之间的差值。 将差值与预定的允许变化量进行比较。 如果差异量大于比较中允许的变化量，则校正与用于预测预测图案的掩模图案数据相对应的设计图案中的单元的放置和布线中的至少一个。

公开(公告)号：US09678561B2

公开(公告)日：2017-06-13

申请号：US14036395

申请日：2013-09-25

申请人： Satoshi Tanaka

发明人： Satoshi Tanaka

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3284 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/159

摘要： In the invention, a first processor that controls operation of a predetermined controlled unit and a second processor are operated in a first mode, a second mode, and a third mode, in the first mode the first processor and second processor are operable respectively, in the second mode respective amounts of power supplied to the first and second processors are lower than that in the first mode, in the third mode respective amounts of power supplied to the first and second processors are an amount between that in the first mode and that in the second mode and at least the predetermined controlled unit is operable, and in the second mode, the first processor puts a process related to the first processor before a process related to the second processor until the second mode is transited to the third mode.