公开(公告)号：US09287292B2

公开(公告)日：2016-03-15

申请号：US12277833

申请日：2008-11-25

申请人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

发明人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/84 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H03K17/6872

摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

摘要翻译： 提供一种具有薄膜BOX-SOI结构并能够实现逻辑电路的高速操作和存储电路的稳定操作的半导体器件。 根据本发明的半导体器件包括半导体支撑衬底，厚度为10nm的绝缘层和半导体层。 在半导体层的上表面中，形成包括第一栅电极并构成逻辑电路的第一场效晶体管。 此外，在半导体层的上表面中，形成包括第二栅电极并构成存储电路的第二场效应晶体管。 在半导体支撑基板中形成具有不同导电类型的至少三个阱区。 在存在阱区的情况下，第一栅电极下方的半导体支撑衬底的区域和第二栅电极下方的半导体支撑衬底的区域彼此电分离。

公开(公告)号：US20090101977A1

公开(公告)日：2009-04-23

申请号：US12253563

申请日：2008-10-17

申请人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

发明人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

IPC分类号： H01L47/00 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

公开(公告)号：US09287400B2

公开(公告)日：2016-03-15

申请号：US13587361

申请日：2012-08-16

申请人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

发明人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

公开(公告)号：US08183115B2

公开(公告)日：2012-05-22

申请号：US13088020

申请日：2011-04-15

申请人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi Ishigaki ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在所述栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比第二升高层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US20090134468A1

公开(公告)日：2009-05-28

申请号：US12277833

申请日：2008-11-25

申请人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

发明人： Ryuta Tsuchiya ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088

CPC分类号： H01L27/1203 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H03K17/6872

摘要： To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate. In the presence of the well regions, a region of the semiconductor support substrate below the first gate electrode and a region of the semiconductor support substrate below the second gate electrode are electrically separated from each other.

摘要翻译： 提供一种具有薄膜BOX-SOI结构并能够实现逻辑电路的高速操作和存储电路的稳定操作的半导体器件。 根据本发明的半导体器件包括半导体支撑衬底，厚度为10nm的绝缘层以及半导体层。 在半导体层的上表面中，形成包括第一栅电极并构成逻辑电路的第一场效晶体管。 此外，在半导体层的上表面中，形成包括第二栅电极并构成存储电路的第二场效应晶体管。 在半导体支撑基板中形成具有不同导电类型的至少三个阱区。 在存在阱区的情况下，第一栅电极下方的半导体支撑衬底的区域和第二栅电极下方的半导体支撑衬底的区域彼此电分离。

公开(公告)号：US08269288B2

公开(公告)日：2012-09-18

申请号：US12253563

申请日：2008-10-17

申请人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

发明人： Toshiaki Iwamatsu ,  Takashi Terada ,  Hirofumi Shinohara ,  Kozo Ishikawa ,  Ryuta Tsuchiya ,  Kiyoshi Hayashi

IPC分类号： H01L29/06

CPC分类号： H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

摘要： An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有通过以高精度形成鳍状半导体部分和栅极电极或通过改善元件之间的特性变化而具有优异的特性的鳍型晶体管。 本发明是一种半导体器件，包括：鳍状半导体部分，其一侧形成有源极区域，在其另一侧形成有漏极区域，以及形成在源极区域和漏极区域之间的栅电极， 翅片状半导体部分，其间具有栅极绝缘膜。 解决根据本发明的问题的一种解决方案是栅电极使用可湿蚀刻的金属材料或硅化物材料。

公开(公告)号：US20090096036A1

公开(公告)日：2009-04-16

申请号：US12248250

申请日：2008-10-09

申请人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

发明人： Takashi ISHIGAKI ,  Ryuta Tsuchiya ,  Yusuke Morita ,  Nobuyuki Sugii ,  Shinichiro Kimura ,  Toshiaki Iwamatsu

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207

摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.

摘要翻译： 提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。 此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。 第一升高层比升高的层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

公开(公告)号：US07812398B2

公开(公告)日：2010-10-12

申请号：US12400324

申请日：2009-03-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US20100084709A1

公开(公告)日：2010-04-08

申请号：US11993862

申请日：2006-06-30

申请人： Ryuta Tsuchiya ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Shinichiro Kimura

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/86

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： When a bulk silicon substrate and an SOI substrate are used separately, a board area is increased and so it is impossible to reduce the size of a semiconductor device as a whole. On the other hand, when an SOI-type MISFET and a bulk-type MISFET are formed on a same substrate, the SOI-type MISFET and the bulk-type MISFET should be formed in separate steps respectively, and thus the process gets complicated. A single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) are used, and well diffusion layer regions, drain regions, gate insulating films and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in same steps. Since the bulk-type MISFET and the SOI-type MISFET can be formed on the same substrate, the board area can be reduced. A simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 当单独使用体硅衬底和SOI衬底时，板面积增加，因此整体上不可能减小半导体器件的尺寸。 另一方面，当在同一衬底上形成SOI型MISFET和体型MISFET时，分别将SOI型MISFET和体型MISFET分别形成，因此工艺变得复杂。 使用通过薄埋入绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的单晶半导体衬底和SOI衬底，以及良好扩散层区域，漏极区域，栅极绝缘膜 并且以相同的步骤形成SOI型MISFET和体型MISFET的栅电极。 由于可以在同一基板上形成体型MISFET和SOI型MISFET，所以可以减小电路板面积。 可以通过制造SOI型MISFET和体型MISFET的制造步骤来实现简单的工艺。

公开(公告)号：US20080258218A1

公开(公告)日：2008-10-23

申请号：US12105226

申请日：2008-04-17

申请人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Yoshinobu Kimura ,  Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/01

CPC分类号： H01L29/045 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

摘要： A MIS transistor having an inclined stacked source/drain structure increased in speed is provided. The MIS transistor comprises: a gate electrode formed on a substrate; a first sidewall insulating film formed on the substrate and along a sidewall of the gate electrode; source/drain semiconductor regions formed on a main surface of the substrate and respectively having one edge positioned under the sidewall of the gate electrode; a first stacked layer formed on the source/drain semiconductor regions and in contact with the first sidewall insulating film; a second sidewall insulating film formed on the stacked layer and in contact with the first sidewall insulating film; and a second stacked layer formed on the first stacked layer and in contact with the second sidewall insulating layer.

摘要翻译： 提供了具有倾斜堆叠的源极/漏极结构的MIS晶体管，其速度提高。 MIS晶体管包括：形成在衬底上的栅电极; 形成在所述基板上并沿着所述栅电极的侧壁的第一侧壁绝缘膜; 源极/漏极半导体区域，形成在基板的主表面上，并且分别具有位于栅电极的侧壁下方的一个边缘; 形成在所述源极/漏极半导体区域上并与所述第一侧壁绝缘膜接触的第一堆叠层; 形成在所述层叠层上并与所述第一侧壁绝缘膜接触的第二侧壁绝缘膜; 以及形成在第一堆叠层上并与第二侧壁绝缘层接触的第二堆叠层。