公开(公告)号：US20060250836A1

公开(公告)日：2006-11-09

申请号：US11125939

申请日：2005-05-09

申请人： S. Herner ,  Christopher Petti

发明人： S. Herner ,  Christopher Petti

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： In a novel rewriteable nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgOx, CrO2, VO, BN, and AlN. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors.

摘要翻译： 在形成于基板上方的新型可重写非易失性存储单元中，二极管与可逆电阻切换材料配对，优选为金属氧化物或氮化物，例如NiO，Nb 2 O > 5，TiO 2，HfO 2，Al 2 O 3，MgO， xO，CrO 2，VO，BN和AlN。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。

公开(公告)号：US20080007989A1

公开(公告)日：2008-01-10

申请号：US11819077

申请日：2007-06-25

申请人： Tanmay Kumar ,  S. Herner ,  Christopher Petti

发明人： Tanmay Kumar ,  S. Herner ,  Christopher Petti

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/00 ,  G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/009 ,  G11C2213/33 ,  H01L27/101

摘要： A method of operating a nonvolatile memory cell includes providing the nonvolatile memory cell comprising a diode which is fabricated in a first resistivity, unprogrammed state, and applying a forward bias to the diode having a magnitude greater than a minimum voltage required for programming the diode to switch the diode to a second resistivity, programmed state. The second resistivity state is lower than the first resistivity state.

摘要翻译： 一种操作非易失性存储单元的方法包括提供非易失性存储单元，该非易失性存储单元包括以第一电阻率，未编程状态制造的二极管，以及将正向偏压施加到具有大于将二极管编程所需的最小电压的二极管的幅度 将二极管切换到第二电阻率，编程状态。 第二电阻率状态低于第一电阻率状态。

公开(公告)号：US20050121742A1

公开(公告)日：2005-06-09

申请号：US10728230

申请日：2003-12-03

申请人： Christopher Petti ,  S. Herner

发明人： Christopher Petti ,  S. Herner

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L27/10 ,  H01L27/102 ,  H01L29/00

CPC分类号： H01L27/101 ,  G11C17/16 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with it. In preferred embodiments, the silicide is cobalt silicide, and the antifuse is preferably silicon oxide, silicon nitride, or silicon oxynitride grown on the cobalt silicide. The junction diode and contact-antifuse unit can be used as a memory cell, which is advantageously used in a monolithic three dimensional memory array.

摘要翻译： 本发明提供了一种垂直取向的结二极管，其具有与其电极之一接触的接触 - 反熔丝单元。 接触 - 反熔丝单元形成在结二极管上方或下方，并且包括形成在其上并与其接触的介电反熔丝层的硅化物。 在优选实施例中，硅化物是硅化钴，反熔丝优选是在硅化钴上生长的氧化硅，氮化硅或氮氧化硅。 结二极管和接触 - 反熔丝单元可用作存储单元，其有利地用于单片三维存储器阵列中。

公开(公告)号：US20060250837A1

公开(公告)日：2006-11-09

申请号：US11395995

申请日：2006-03-31

申请人： S. Herner ,  Tanmay Kumar ,  Christopher Petti

发明人： S. Herner ,  Tanmay Kumar ,  Christopher Petti

IPC分类号： G11C11/00

CPC分类号： H01L27/249 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy, HFxOy, AlxOy, MgxOy, CoxOy, CrxOy, VxOy, ZnxOy, ZrxOy, BxNy, and AlxNy. In preferred embodiments, the diode is formed as a vertical pillar disposed between conductors. Multiple memory levels can be stacked to form a monolithic three dimensional memory array. In some embodiments, the diode comprises germanium or a germanium alloy, which can be deposited and crystallized at relatively low temperatures, allowing use of aluminum or copper in the conductors. The memory cell of the present invention can be used as a rewriteable memory cell or a one-time-programmable memory cell, and can store two or more data states.

摘要翻译： 在形成在衬底上方的新型非易失性存储单元中，二极管与可逆电阻切换材料配对，优选地为金属氧化物或氮化物，例如Ni x O y O y， 铌，x O y，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，，SUB，SUB 其中，O x Y y O y，Y x O y，Y O x O x，X x O，O x O，X x O， y，x，x，y，y，x，y，x，y，x， / SUB＆gt; Y＆gt;和＆lt; N＆gt; N＆lt; / SUB＆gt;。 在优选实施例中，二极管形成为设置在导体之间的垂直支柱。 可以堆叠多个存储器级别以形成单片三维存储器阵列。 在一些实施例中，二极管包括锗或锗合金，其可以在相对低的温度下沉积和结晶，从而允许在导体中使用铝或铜。 本发明的存储单元可以用作可重写存储单元或一次可编程存储单元，并且可以存储两个或多个数据状态。

公开(公告)号：US20070072360A1

公开(公告)日：2007-03-29

申请号：US11496986

申请日：2006-07-31

申请人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

发明人： Tanmay Kumar ,  S.B. Herner ,  Roy Scheuerlein ,  Christopher Petti

IPC分类号： H01L21/8234

CPC分类号： G11C11/5692 ,  G11C13/0069 ,  G11C17/14 ,  G11C17/165 ,  G11C2013/0073 ,  H01L27/101

摘要： A nonvolatile memory cell comprising a diode formed of semiconductor material can store memory states by changing the resistance of the semiconductor material by application of a set pulse (decreasing resistance) or a reset pulse (increasing resistance.) In preferred embodiments, set pulses are applied with the diode under forward bias, while reset pulses are applied with the diode in reverse bias. By switching resistivity of the semiconductor material of the diode, a memory cell can be either one-time programmable or rewriteable, and can achieve two, three, four, or more distinct data states.

摘要翻译： 包括由半导体材料形成的二极管的非易失性存储单元可以通过施加设置脉冲（降低电阻）或复位脉冲（增加电阻）来改变半导体材料的电阻来存储存储器状态。在优选实施例中，施加设定脉冲 二极管在正向偏置下，而复位脉冲以二极管反向施加。 通过切换二极管的半导体材料的电阻率，存储器单元可以是一次性可编程的或可重写的，并且可以实现两个，三个，四个或更多个不同的数据状态。

公开(公告)号：US20070007579A1

公开(公告)日：2007-01-11

申请号：US11179095

申请日：2005-07-11

申请人： Roy Scheuerlein ,  Christopher Petti

发明人： Roy Scheuerlein ,  Christopher Petti

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  G11C11/5614 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0011 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L21/84 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/685 ,  H01L29/786 ,  H01L29/8605 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A nonvolatile memory cell comprising a switchable resistor memory element and a thin-film three-terminal switching device, preferably a MOSFET, in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high-resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device. Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.

摘要翻译： 一种包括可切换电阻存储元件和薄膜三端开关器件（优选为MOSFET）的非易失性存储单元。 可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。 它在两个状态之间切换，并且通过提供通过三端开关器件的合适电流来感测其电阻状态（并因此感测单元的数据状态）。 本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底之上。

公开(公告)号：US20070007577A1

公开(公告)日：2007-01-11

申请号：US11175688

申请日：2005-07-06

申请人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

发明人： Abhijit Bandyopadhyay ,  Christopher Petti ,  Tanmay Kumar

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

摘要： An integrated circuit is provided including at least one memory cell. Such memory cell, in turn, includes a transistor and a capacitor. The transistor includes a source, a drain, and a gate. Further, the capacitor includes a well and a gate. The gate of the transistor remains in communication with the gate of the capacitor. In various other embodiments, the memory cell includes a transistor and a capacitor including wells of differing types (e.g. P-type, N-type). In such embodiments, the well of the transistor abuts the well of the capacitor. In still further embodiments, for a more compact design, a diffusion region of the transistor is situated less than 2.5 μm from a diffusion region of the capacitor.

摘要翻译： 提供了包括至少一个存储单元的集成电路。 这样的存储单元又包括晶体管和电容器。 晶体管包括源极，漏极和栅极。 此外，电容器包括阱和栅极。 晶体管的栅极保持与电容器的栅极通信。 在各种其他实施例中，存储单元包括晶体管和包括不同类型的阱（例如，P型，N型）的电容器。 在这样的实施例中，晶体管的阱邻接电容器的阱。 在另外的实施例中，为了更紧凑的设计，晶体管的扩散区域距离电容器的扩散区域小于2.5μm。

公开(公告)号：US20060249735A1

公开(公告)日：2006-11-09

申请号：US11484757

申请日：2006-07-12

申请人： Andrew Walker ,  Christopher Petti

发明人： Andrew Walker ,  Christopher Petti

IPC分类号： H01L29/04 ,  H01L29/80 ,  H01L29/76

CPC分类号： H01L27/1128 ,  G11C17/12 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11286 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11803 ,  H01L27/1203 ,  H01L27/1214 ,  H01L29/66825

摘要： There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

公开(公告)号：US5654915A

公开(公告)日：1997-08-05

申请号：US663603

申请日：1996-06-14

申请人： Andre Stolmeijer ,  Christopher Petti

发明人： Andre Stolmeijer ,  Christopher Petti

IPC分类号： G11C8/14 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C11/412 ,  G11C8/14

摘要： The present invention relates to a solid-state bi-stable circuit functioning as a six-bulk transistor static memory cell, the circuit comprising a plurality of bitlines and at least a first and second reference line, all of which are positioned in parallel with a plurality of wordlines. The circuit further comprises a plurality of transistors including a first and second load transistor, a first and a second pull-down transistor and a first and a second access transistor, in which each of the plurality of transistors includes a gate, source and drain. The gates of the plurality of transistors are positioned in parallel to minimize area usage.

摘要翻译： 本发明涉及用作六体晶体管静态存储单元的固态双稳电路，该电路包括多个位线和至少第一和第二参考线，所有这些都与 多个字线。 该电路还包括多个晶体管，其包括第一和第二负载晶体管，第一和第二下拉晶体管以及第一和第二存取晶体管，其中多个晶体管中的每一个包括栅极，源极和漏极。 多个晶体管的栅极并联放置以最小化区域使用。

公开(公告)号：US07629247B2

公开(公告)日：2009-12-08

申请号：US11786620

申请日：2007-04-12

申请人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

发明人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

IPC分类号： H01L21/4763

CPC分类号： H01L29/6609 ,  H01L21/76802 ,  H01L27/101 ,  H01L27/1021 ,  H01L29/868

摘要： A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements.

摘要翻译： 公开了一种使用镶嵌制造技术形成三维非易失性存储阵列的方法。 形成底部的一组导体，并在其上形成一组重掺杂半导体材料的第一柱形元件。 模具由具有与第一柱形元件自对准的柱形开口的绝缘材料形成，并且第二半导体沉积在模具上以形成与第一柱状元件对准的第二柱状元件。 可以通过形成具有与柱状元件对准的沟槽开口的另一个绝缘材料模具，然后用导电材料填充沟槽，以形成连接到柱状元件的导体，来进一步处理所形成的柱元件。