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    Memory device
    1.
    发明授权
    Memory device 有权

    公开(公告)号：US11450684B2

    公开(公告)日：2022-09-20

    申请号：US17007141

    申请日：2020-08-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Joonsung Lim

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

    Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20250120080A1

    公开(公告)日：2025-04-10

    申请号：US18666888

    申请日：2024-05-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junhyoung Kim ,  Bumkyu Kang ,  Sehoon Lee ,  Sukkang Sung

    IPC: H10B43/27 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10B80/00

    Abstract: A semiconductor device includes a first substrate structure, and a second substrate structure connected to the first substrate structure and including circuit elements and second bonding metal layers. The first substrate structure includes gate electrodes stacked along a first direction, a supporter layer on the gate electrodes, channel structures extending along the first direction while penetrating the gate electrodes, separation regions extending in the first direction and a second direction by penetrating through the gate electrodes, and first bonding metal layers connected to the second bonding metal layers. The separation regions respectively include first regions spaced apart from each other along the second direction and a second region surrounding side surfaces of the first regions and extending in the second direction. The first regions and the channel structures penetrate the supporter layer, and a portion of a lower surface of the supporter layer is in contact with the second region.

    Semiconductor device and electronic system including the same
    4.
    发明授权
    Semiconductor device and electronic system including the same 有权

    公开(公告)号：US12160992B2

    公开(公告)日：2024-12-03

    申请号：US17563547

    申请日：2021-12-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jiyoung Kim ,  Bumkyu Kang ,  Joonsung Lim ,  Sukkang Sung

    IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

    Abstract: A semiconductor device includes a substrate having a cell region and a connection region, a first stack structure with a plurality of first gate layers and a plurality of first interlayer insulating layers, and a second stack structure with a plurality of second gate layers and a plurality of second interlayer insulating layers. Each of the first gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. Each of the second gate layers includes a central portion in the cell region of the substrate and an end portion in the connection region of the substrate. A thickness difference between the end and central portions of each first gate layer is different from a thickness difference between the end and central portions of each second gate layer.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20250048636A1

    公开(公告)日：2025-02-06

    申请号：US18652120

    申请日：2024-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bumkyu Kang ,  Jiyoung Kim ,  Sukkang Sung

    IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

    Abstract: A semiconductor device includes a first semiconductor structure including a substrate, circuit elements, and circuit interconnection lines, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a plate layer, first gate electrodes stacked on the plate layer and spaced apart from each other in a first direction, separation regions penetrating through the first gate electrodes and extending in a second direction, first channel structures spaced apart from the separation regions in a third direction, penetrating through the first gate electrodes, and extending in the first direction, and dummy structures contacting the separation regions, penetrating through the first gate electrodes, and extending in the first direction. The first channel structures and the dummy structures respectively have a circular shape in plan view, and the separation regions are in contact with at least portions of respective side surfaces of the dummy structures.

    Semiconductor devices and data storage system including the same
    7.
    发明授权
    Semiconductor devices and data storage system including the same 有权

    公开(公告)号：US12082415B2

    公开(公告)日：2024-09-03

    申请号：US17375273

    申请日：2021-07-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jimo Gu ,  Bumkyu Kang ,  Sungmin Hwang

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

    Three-dimensional semiconductor memory device
    9.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11641738B2

    公开(公告)日：2023-05-02

    申请号：US17021416

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

    IPC: H01L27/11539 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11543 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11578

    Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

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