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    Three-dimensional semiconductor memory device
    2.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11289503B2

    公开(公告)日：2022-03-29

    申请号：US16773084

    申请日：2020-01-27

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Byungjin Lee ,  Dong-sik Lee ,  Joon-Sung Lim

    IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

    摘要： A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

    Memory device
    6.
    发明授权
    Memory device 有权

    公开(公告)号：US11450684B2

    公开(公告)日：2022-09-20

    申请号：US17007141

    申请日：2020-08-31

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Joonsung Lim

    IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

    摘要： A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

    Three-dimensional semiconductor memory device
    8.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11641738B2

    公开(公告)日：2023-05-02

    申请号：US17021416

    申请日：2020-09-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

    IPC分类号： H01L27/11539 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11543 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11578

    摘要： A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.