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    Three-dimensional semiconductor memory device and a method of fabricating the same
    1.
    发明授权
    Three-dimensional semiconductor memory device and a method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US09117923B2

    公开(公告)日：2015-08-25

    申请号：US13830208

    申请日：2013-03-14

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Sunil Shim ,  Jaehoon Jang ,  Hansoo Kim ,  Sungmin Hwang ,  Wonseok Cho ,  Jinsoo Lim

    IPC分类号： H01L29/792 ,  H01L27/115

    CPC分类号： H01L29/7926 ,  H01L27/11556 ,  H01L27/11582

    摘要： A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer, and forming a conductive pattern.

    摘要翻译： 一种形成半导体存储器件的方法包括在衬底上堆叠多个交替的第一绝缘层和第一牺牲层以形成第一多层结构，通过第一多层结构形成第一孔，在第一孔中形成第一半导体图案 在所述第一多层结构上堆叠多个交替的第二绝缘层和第二牺牲层以形成第二多层结构，通过所述第二多层结构形成与所述第一孔对准的第二孔，在所述第二多层结构中形成第二半导体图案 形成沟槽，以在第一和第二半导体图案的一侧露出第一绝缘层和第二绝缘层的侧壁，去除第一和第二牺牲层的至少一部分以形成多个凹陷区域，形成信息存储器 层，形成导电图案。

    Semiconductor devices and data storage system including the same
    4.
    发明授权
    Semiconductor devices and data storage system including the same 有权

    公开(公告)号：US12082415B2

    公开(公告)日：2024-09-03

    申请号：US17375273

    申请日：2021-07-14

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jimo Gu ,  Bumkyu Kang ,  Sungmin Hwang

    IPC分类号： H10B43/27 ,  H10B41/27

    CPC分类号： H10B43/27 ,  H10B41/27

    摘要： A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

    Integrated circuit device and method of fabricating the same
    5.
    发明授权
    Integrated circuit device and method of fabricating the same 有权

    公开(公告)号：US11251196B2

    公开(公告)日：2022-02-15

    申请号：US16749255

    申请日：2020-01-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jaeho Ahn ,  Woosung Yang ,  Joonsung Lim ,  Sungmin Hwang

    IPC分类号： H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

    摘要： An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.