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公开(公告)号：US20240321841A1
公开(公告)日：2024-09-26
申请号：US18609255
申请日：2024-03-19
发明人： Hwanjoo PARK , Jaechoon KIM , Sunggu KANG , Taehwan KIM
IPC分类号： H01L25/10 , H01L23/00 , H01L23/31 , H01L23/373 , H01L23/498 , H01L23/538 , H01L25/065
CPC分类号： H01L25/105 , H01L23/3128 , H01L23/3736 , H01L23/49816 , H01L23/5383 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/1094
摘要： The disclosure provides a semiconductor package including a first wiring structure including a first wiring, a first semiconductor chip on the first wiring structure, a molding member surrounding the first semiconductor chip, a second wiring structure on an upper surface of the molding member and including a second wiring and a heat conductive metal, a second semiconductor chip on an upper surface of the second wiring structure, a plurality of first bumps between the second wiring structure and the second semiconductor chip, an underfill layer covering the plurality of first bumps, and a first thermal interface material (TIM) on an upper surface of the heat conductive metal, the heat conductive metal not overlapping the plurality of first bumps in the vertical direction.
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公开(公告)号：US20240332150A1
公开(公告)日：2024-10-03
申请号：US18401872
申请日：2024-01-02
发明人： Hwanjoo PARK , Sunggu KANG , Jaechoon KIM
IPC分类号： H01L23/498 , H01L23/00 , H01L23/367 , H01L23/48 , H01L25/065
CPC分类号： H01L23/49822 , H01L23/367 , H01L23/481 , H01L23/49816 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0652 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/1431
摘要： A semiconductor package includes a first redistribution wiring layer having first redistribution wirings; a first lower semiconductor chip and a second lower semiconductor chip spaced apart from each other on the first redistribution wiring layer; a sealing member covering the first lower semiconductor chip and the second lower semiconductor chip on the first redistribution wiring layer; a plurality of conductive vias penetrating the sealing member between the first lower semiconductor chip and the second lower semiconductor chip; a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of conductive vias; an upper semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings; and a first heat dissipation block and a second heat dissipation block respectively disposed on the first lower semiconductor chip and the second lower semiconductor chip.
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公开(公告)号：US20240072020A1
公开(公告)日：2024-02-29
申请号：US18188627
申请日：2023-03-23
发明人： JAE CHOON KIM , Hwanjoo PARK , Sunggu KANG , SUNG-HO MUN
IPC分类号： H01L25/10 , H10B80/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/00
CPC分类号： H01L25/105 , H10B80/00 , H01L23/3157 , H01L23/3135 , H01L23/49838 , H01L23/5386 , H01L23/49822 , H01L24/08 , H01L24/16 , H01L24/48 , H01L2224/08112 , H01L2224/16227 , H01L2224/48221 , H01L2924/1436 , H01L2924/1432 , H01L2225/1058
摘要： A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.
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公开(公告)号：US20240145360A1
公开(公告)日：2024-05-02
申请号：US18244997
申请日：2023-09-12
发明人： Hwanjoo PARK , Jaechoon KIM , Sunggu KANG , Eunho CHO , Taehwan KIM , Jonggyu LEE
IPC分类号： H01L23/498 , H01L23/00 , H01L25/10
CPC分类号： H01L23/49811 , H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2225/1023 , H01L2225/1041 , H01L2924/1434
摘要： A semiconductor package includes a first redistribution wiring layer having first redistribution wirings, a first semiconductor chip on the first redistribution wiring layer and having a first thickness from the first redistribution wiring layer, a second semiconductor chip disposed on the first redistribution wiring layer spaced apart from the first semiconductor chip and having a second thickness from the first redistribution wiring layer smaller than the first thickness, a sealing member covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer, a plurality of conductive vias provided in the sealing member and electrically connected to the first redistribution wirings, a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the conductive vias, and at least one third semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings.
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公开(公告)号：US20230307318A1
公开(公告)日：2023-09-28
申请号：US18066861
申请日：2022-12-15
发明人： Jonggyu LEE , Sunggu KANG , Jaechoon KIM , Taehwan KIM , Hwanjoo PARK , Kyungsuk OH
IPC分类号： H01L23/473 , H01L25/18 , H01L23/538 , H01L23/31
CPC分类号： H01L23/473 , H01L25/18 , H01L23/5385 , H01L23/3128
摘要： A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.
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