公开(公告)号：US20240321841A1

公开(公告)日：2024-09-26

申请号：US18609255

申请日：2024-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Jaechoon KIM ,  Sunggu KANG ,  Taehwan KIM

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1094

Abstract: The disclosure provides a semiconductor package including a first wiring structure including a first wiring, a first semiconductor chip on the first wiring structure, a molding member surrounding the first semiconductor chip, a second wiring structure on an upper surface of the molding member and including a second wiring and a heat conductive metal, a second semiconductor chip on an upper surface of the second wiring structure, a plurality of first bumps between the second wiring structure and the second semiconductor chip, an underfill layer covering the plurality of first bumps, and a first thermal interface material (TIM) on an upper surface of the heat conductive metal, the heat conductive metal not overlapping the plurality of first bumps in the vertical direction.

公开(公告)号：US20240321673A1

公开(公告)日：2024-09-26

申请号：US18379286

申请日：2023-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggu KANG ,  JAE CHOON KIM ,  SUNG-HO Mun ,  Hwanjoo Park

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution layer structure, a semiconductor structure on the redistribution layer structure, at least one heat dissipation structure on the semiconductor structure, where the at least one heat dissipation structure may include a first epoxy molding compound, a molding material for molding the semiconductor structure and the at least one heat dissipation structure, on the redistribution layer structure, where the molding material may include a second epoxy molding compound, where the first epoxy molding compound may have higher thermal conductivity than the second epoxy molding compound.

公开(公告)号：US20240310103A1

公开(公告)日：2024-09-19

申请号：US18668576

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin JEONG ,  Sunggu KANG ,  Bongsu SON ,  Yongsun SONG ,  Kwanyeol LEE

IPC: F25C1/25 ,  F25C1/24 ,  F25C5/08

CPC classification number: F25C1/25 ,  F25C1/24 ,  F25C5/08 ,  F25C2600/00

Abstract: A refrigerator including: a main body including at least one storage compartment; a temperature sensor arrangeable in the main body; an ice making device including an ice tray arrangeable in the at least one storage compartment such that while the ice tray is arranged in the storage compartment, the ice tray allows ice to be formed therein, and an ice separator configured to separate the ice formed from the ice tray; a cooling device configured to cool the at least one storage compartment; a water supply device configured to supply water to the ice tray that forms the ice; and a controller configured to, based on a temperature value detected by the temperature sensor arranged in the main body being greater than a preset value, control the water supply device so that no water is supplied to the ice tray and control the ice making device to perform an inspection cycle to inspect the ice separator.

公开(公告)号：US20250062279A1

公开(公告)日：2025-02-20

申请号：US18594300

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggu KANG ,  Jae Choon KIM ,  Sung-Ho MUN ,  Hwanjoo PARK

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising an interposer, a first semiconductor die below the interposer, and a first dummy die, a second dummy die, and a second semiconductor die over the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer. The first semiconductor die overlaps the second semiconductor die. The second semiconductor die is between the first dummy die and the second dummy die.

公开(公告)号：US20240332150A1

公开(公告)日：2024-10-03

申请号：US18401872

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Sunggu KANG ,  Jaechoon KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings; a first lower semiconductor chip and a second lower semiconductor chip spaced apart from each other on the first redistribution wiring layer; a sealing member covering the first lower semiconductor chip and the second lower semiconductor chip on the first redistribution wiring layer; a plurality of conductive vias penetrating the sealing member between the first lower semiconductor chip and the second lower semiconductor chip; a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the plurality of conductive vias; an upper semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings; and a first heat dissipation block and a second heat dissipation block respectively disposed on the first lower semiconductor chip and the second lower semiconductor chip.

公开(公告)号：US20240072020A1

公开(公告)日：2024-02-29

申请号：US18188627

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE CHOON KIM ,  Hwanjoo PARK ,  Sunggu KANG ,  SUNG-HO MUN

IPC: H01L25/10 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/105 ,  H10B80/00 ,  H01L23/3157 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/08112 ,  H01L2224/16227 ,  H01L2224/48221 ,  H01L2924/1436 ,  H01L2924/1432 ,  H01L2225/1058

Abstract: A semiconductor package may include a lower structure, a first semiconductor chip on the lower structure, the first semiconductor chip including a hot spot, a second semiconductor chip horizontally spaced apart from the first semiconductor chip on the lower structure, and a connection chip in the lower structure and connecting the first and second semiconductor chips to each other. The hot spot may vertically overlap the connection chip.

公开(公告)号：US20240413038A1

公开(公告)日：2024-12-12

申请号：US18402558

申请日：2024-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwanjoo PARK ,  Jae Choon KIM ,  Sunggu KANG ,  Taehwan KIM

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A stacked semiconductor package includes: a first semiconductor package that includes a first region and a second region and includes a semiconductor chip including a first element at the first region and a second element at the second region; a second semiconductor package on the first region of the first semiconductor package; and a member for heat dissipation at the second region of the first semiconductor package and overlapping at least a portion of the second element in a vertical direction perpendicular to an in-plane direction of the first semiconductor package.

公开(公告)号：US20240145360A1

公开(公告)日：2024-05-02

申请号：US18244997

申请日：2023-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwanjoo PARK ,  Jaechoon KIM ,  Sunggu KANG ,  Eunho CHO ,  Taehwan KIM ,  Jonggyu LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2924/1434

Abstract: A semiconductor package includes a first redistribution wiring layer having first redistribution wirings, a first semiconductor chip on the first redistribution wiring layer and having a first thickness from the first redistribution wiring layer, a second semiconductor chip disposed on the first redistribution wiring layer spaced apart from the first semiconductor chip and having a second thickness from the first redistribution wiring layer smaller than the first thickness, a sealing member covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer, a plurality of conductive vias provided in the sealing member and electrically connected to the first redistribution wirings, a second redistribution wiring layer disposed on the sealing member and having second redistribution wirings electrically connected to the conductive vias, and at least one third semiconductor chip disposed on the second redistribution wiring layer and electrically connected to the second redistribution wirings.

公开(公告)号：US20230307318A1

公开(公告)日：2023-09-28

申请号：US18066861

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggyu LEE ,  Sunggu KANG ,  Jaechoon KIM ,  Taehwan KIM ,  Hwanjoo PARK ,  Kyungsuk OH

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/473 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/3128

Abstract: A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.