公开(公告)号：US20210375831A1

公开(公告)日：2021-12-02

申请号：US17399233

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Kyungsuk OH ,  Hyunki KIM ,  Yongkwan LEE ,  Sangsoo KIM ,  Seungkon MOK ,  Junyoung OH ,  Changyoung YOO

IPC: H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.

公开(公告)号：US20230307318A1

公开(公告)日：2023-09-28

申请号：US18066861

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggyu LEE ,  Sunggu KANG ,  Jaechoon KIM ,  Taehwan KIM ,  Hwanjoo PARK ,  Kyungsuk OH

IPC: H01L23/473 ,  H01L25/18 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/473 ,  H01L25/18 ,  H01L23/5385 ,  H01L23/3128

Abstract: A semiconductor package includes a package substrate; an interposer on the package substrate; a first semiconductor chip on the interposer; at least one second semiconductor chip on the interposer; a molding layer extending around the first semiconductor chip and the at least one second semiconductor chip; a barrier layer on the upper surface of the molding layer; a separation wall on the barrier layer, the separation wall configured to define a first cooling space adjacent the first semiconductor chip and a second cooling space adjacent the at least one second semiconductor chip; and a heat dissipation structure on the separation wall, wherein the heat dissipation structure provides a cooling channel through which the cooling fluid flows.

公开(公告)号：US20240014166A1

公开(公告)日：2024-01-11

申请号：US18218886

申请日：2023-07-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngdeuk KIM ,  Jaechoon KIM ,  Taehwan KIM ,  Kyungsuk OH ,  Heejung Hwang

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00 ,  H01L25/00

CPC classification number: H01L24/73 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05155 ,  H01L2224/05073 ,  H01L2224/05564 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/05647 ,  H01L2224/80359 ,  H01L2924/0544 ,  H01L2924/059 ,  H01L2224/06505 ,  H01L2224/08145 ,  H01L2224/13111 ,  H01L2224/13109 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/13139 ,  H01L2224/13118 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2924/014 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32013 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/80357 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2224/9211 ,  H01L2224/92222 ,  H01L2224/92242 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9222

Abstract: A semiconductor package including: a lower chip; a chip structure including stacked semiconductor chips; and an adhesive film, the semiconductor chips include first bonding chips bonded to each other by bumps and second bonding chips directly bonded to each other, the first bonding chips include: a first bonding lower chip including a first bonding upper pad; and a first bonding upper chip on the first bonding lower chip and including a first bonding lower pad, the second bonding chips include: a second bonding lower chip including a second bonding upper insulating layer and a second bonding upper pad; and a second bonding upper chip on the second bonding lower chip and including a second bonding lower insulating layer, and a second bonding lower pad, and the adhesive film surrounds side surfaces of the bumps, fills a region between the first bonding lower and upper chips, and protrudes from the region.

公开(公告)号：US20210066244A1

公开(公告)日：2021-03-04

申请号：US16821342

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a package substrate; a first semiconductor chip on the package substrate; a second semiconductor chip on an upper surface of the first semiconductor chip; an insulating layer on surfaces of the first semiconductor chip and the second semiconductor chip; a heat dissipation member on the insulating layer such that the heat dissipation member includes a region on an upper surface of the first semiconductor chip on which the second semiconductor chip is not disposed, and a region on an upper surface of the second semiconductor chip; a molding member on the package substrate and encapsulating the first semiconductor chip, the second semiconductor chip, and the heat dissipation member such that the molding member exposes at least a portion of an upper surface of the heat dissipation member; and a reinforcing member on the heat dissipation member and the molding member.

公开(公告)号：US20240186290A1

公开(公告)日：2024-06-06

申请号：US18236024

申请日：2023-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehwan KIM ,  Youngdeuk KIM ,  Jaechoon KIM ,  Kyungsuk OH ,  Jonggyu LEE ,  Mina CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes electrically connected first to third semiconductor chips, stacked in a vertical direction; an encapsulant on the first semiconductor chip and encapsulating a portion of each of the semiconductor chips; and external connection bumps below the first semiconductor chip and being electrically connected to the semiconductor chips, wherein the semiconductor chips each include a plurality of lower pads, the first and second semiconductor chips each include a plurality of upper pads including a first group of upper pads and a second group of upper pads, and through-electrodes electrically respectively connecting the upper pads and the lower pads, and the through-electrodes include a first group of through-electrodes respectively connected to the first group of upper pads, and a second group of through-electrodes connected to upper pads that are electrically connected to each other of the second group of upper pads.

公开(公告)号：US20230178450A1

公开(公告)日：2023-06-08

申请号：US17892252

申请日：2022-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun JO ,  Jaemin JUNG ,  Jaechoon KIM ,  Seunggeol RYU ,  Kyungsuk OH

IPC: H01L23/367 ,  H01L23/528

CPC classification number: H01L23/367 ,  H01L23/5283

Abstract: A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.

公开(公告)号：US20210057380A1

公开(公告)日：2021-02-25

申请号：US16816593

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunchul KIM ,  Kyungsuk OH ,  Taehun KIM ,  Pyoungwan KIM ,  Soohwan LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.