公开(公告)号：US20240250000A1

公开(公告)日：2024-07-25

申请号：US18468317

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk YIM ,  Wandon KIM ,  Hyunbae LEE ,  Hyoseok CHOI ,  Sunghwan KIM ,  Junki PARK

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a source/drain pattern on the active pattern, an active contact on the source/drain pattern; a lower power line in the substrate, a lower contact that vertically connects the active contact to the lower power line, a conductive layer between the lower contact and the lower power line, and a power delivery network layer on a bottom surface of the substrate. The conductive layer may include silicon (Si) and a first element. The first element may include a transition metal or a metalloid. A concentration of the first element may decrease in a direction from the lower contact toward the lower power line.

公开(公告)号：US20240128319A1

公开(公告)日：2024-04-18

申请号：US18322234

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunwoo KIM ,  Wandon KIM ,  Jaeseoung PARK ,  Hyunbae LEE ,  Jeonghyuk YIM

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/518 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a first conductive pattern on a substrate, a second conductive pattern surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulating structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern extending in a vertical direction through the upper insulating structure. The upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension portion extending from a local region of the main plug portion toward the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction.

公开(公告)号：US20200243374A1

公开(公告)日：2020-07-30

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon CHOI ,  Jaeung KOO ,  Kwansung KIM ,  Bo Yun KIM ,  Wandon KIM ,  Boun YOON ,  Jeonghyuk YIM ,  Yeryung JEON

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US20240145313A1

公开(公告)日：2024-05-02

申请号：US18407020

申请日：2024-01-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk YIM ,  Kang Ill SEO

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823487 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/66666 ,  H01L29/7827

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the Pt fin structures.

公开(公告)号：US20190198498A1

公开(公告)日：2019-06-27

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Wandon KIM ,  Jeonghyuk YIM ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.