NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    NITRIDE BASED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    基于氮化物的半导体器件及其制造方法

    公开(公告)号:US20130168688A1

    公开(公告)日:2013-07-04

    申请号:US13728157

    申请日:2012-12-27

    Abstract: A nitride based semiconductor device includes a first metallic junction layer, a Schottky junction layer on the first metallic junction layer, a first group III nitride semiconductor layer on the Schottky junction layer, a first insulating pattern layer on the first group III nitride semiconductor layer, the first insulating layer pattern including curved protrusions, a second group III nitride semiconductor layer laterally grown on the first group III nitride semiconductor layer, a first type group III nitride semiconductor layer on the second group III nitride semiconductor layer, the first type group III nitride semiconductor layer being simultaneously doped with aluminum (Al) and silicon (Si), an ohmic junction layer formed on the first type group III nitride semiconductor layer, a second metallic junction layer on the ohmic junction layer, and a metallic supporting substrate on the second metallic junction layer.

    Abstract translation: 氮化物基半导体器件包括第一金属结层,第一金属结层上的肖特基结层,肖特基结层上的第一III族氮化物半导体层,第一III族氮化物半导体层上的第一绝缘图案层, 第一绝缘层图案包括弯曲突起,在第一III族氮化物半导体层上横向生长的第二III族氮化物半导体层,第二III族氮化物半导体层上的第一类型III族氮化物半导体层,第一类型III族氮化物 半导体层同时掺杂有铝(Al)和硅(Si),形成在第一类型III族氮化物半导体层上的欧姆结层,欧姆结层上的第二金属结层和第二金属支撑衬底 金属结层。

    ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL CONVERSION METHOD USING THE SAME

    公开(公告)号:US20230231571A1

    公开(公告)日:2023-07-20

    申请号:US18150636

    申请日:2023-01-05

    CPC classification number: H03M1/825 H03M1/182 H03M1/462

    Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

    AMPLIFIER AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20230223906A1

    公开(公告)日:2023-07-13

    申请号:US17979148

    申请日:2022-11-02

    CPC classification number: H03F3/45269 H03F2200/451

    Abstract: An amplifier and an electronic system including the same are provided. An amplifier includes a first NMOS transistor configured to receive a first input, a second NMOS transistor configured to receive a second input, the second NMOS transistor including a source connected to a source of the first NMOS transistor, a first resistor including a first end connected to a drain of the first NMOS transistor and a second end connected to a first output, a second resistor including a first end connected to a drain of the second NMOS transistor, and a second end connected to a second output, and the amplifier is configured to generate the first output and the second output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.

    DIVERSITY AMP MODULE AND APPARATUS COMPRISING THE SAME
    6.
    发明申请
    DIVERSITY AMP MODULE AND APPARATUS COMPRISING THE SAME 有权
    多样化放大器模块和包含该模块的装置

    公开(公告)号:US20160020738A1

    公开(公告)日:2016-01-21

    申请号:US14800841

    申请日:2015-07-16

    Abstract: An amplifying module having one input terminal and one output terminal and passing an antenna signal input through the input terminal towards the output terminal. The amplifying module includes a first switch connected to the input terminal, a plurality of filters selectable by the first switch, a plurality of amplifiers respectively connected to the plurality of filters and amplifying a signal that has passed through the filters, and a second switch for connecting the amplified signal to the output terminal.

    Abstract translation: 一种放大模块,具有一个输入端和一个输出端,并将通过输入端输入的天线信号传送到输出端。 放大模块包括连接到输入端的第一开关,由第一开关选择的多个滤波器,分别连接到多个滤波器并放大已经通过滤波器的信号的多个放大器,以及第二开关, 将放大的信号连接到输出端子。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20150162427A1

    公开(公告)日:2015-06-11

    申请号:US14458288

    申请日:2014-08-13

    CPC classification number: H01L29/7787 H01L29/1029 H01L29/2003 H01L29/66462

    Abstract: A semiconductor device may include: a first semiconductor layer having a first band gap; a second semiconductor layer including first and second regions separately disposed on an upper surface of the first semiconductor layer and having a second band gap wider than the first band gap; and a third semiconductor layer disposed between the first and second regions of the second semiconductor layer, extending up to at least a portion of the first semiconductor layer. The third semiconductor layer may have a channel region doped with an impurity.

    Abstract translation: 半导体器件可以包括:具有第一带隙的第一半导体层; 第二半导体层,包括分别设置在第一半导体层的上表面上并具有比第一带隙宽的第二带隙的第一和第二区域; 以及第三半导体层,设置在所述第二半导体层的所述第一和第二区之间,延伸到所述第一半导体层的至少一部分。 第三半导体层可以具有掺杂有杂质的沟道区。

    SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE

    公开(公告)号:US20170264334A1

    公开(公告)日:2017-09-14

    申请号:US15453577

    申请日:2017-03-08

    CPC classification number: H04B1/401 H04B1/0067 H04W88/06

    Abstract: Provided are a semiconductor device and an operating method thereof. The semiconductor device includes a mode controller configured to output a first control signal in a first communication mode, and output a second control signal in a second communication mode which is different from the first communication mode; and a configurable circuit configured to generate a first output signal to be transmitted to a first type analog-to-digital converter (ADC) in the first communication mode, and generate a second output signal using a second type ADC in the second communication mode, wherein the configurable circuit comprises a switching circuit configured to change a circuit configuration to a first circuit configuration for generating a first output signal in the first communication mode or to a second circuit configuration for generating a second output signal in the second communication mode, depending on the first control signal or the second control signal received from the mode controller.

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