公开(公告)号：US20220059466A1

公开(公告)日：2022-02-24

申请号：US17198359

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20240071899A1

公开(公告)日：2024-02-29

申请号：US18450836

申请日：2023-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyuho KANG ,  Hyungjun PARK ,  Seonghoon BAE ,  Sanghyuck OH ,  Kwangok JEONG ,  Juil CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49866 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5383 ,  H01L25/105 ,  H01L24/16

Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.

公开(公告)号：US20240312923A1

公开(公告)日：2024-09-19

申请号：US18677075

申请日：2024-05-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Solji SONG ,  Byeongchan KIM ,  Jumyong PARK ,  Jinho AN ,  Chungsun LEE ,  Jeonggi JIN ,  Juil CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227

Abstract: A semiconductor package includes an interposer having a first surface and a second surface opposite to the first surface and including a plurality of bonding pads, and first and second semiconductor devices on the interposer. Each of the plurality of bonding pads includes a first pad pattern provided to be exposed from the first surface and having a first width and a second pad pattern provided on the first pad pattern and having a second width greater than the first width.

公开(公告)号：US20230111136A1

公开(公告)日：2023-04-13

申请号：US17966864

申请日：2022-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji Song ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20250038081A1

公开(公告)日：2025-01-30

申请号：US18734529

申请日：2024-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho PARK ,  Unbyoung KANG ,  Seonghoon BAE ,  Jaemok JUNG ,  Juil CHOI ,  Taeoh HA

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region and including first redistribution wirings, a semiconductor chip disposed on the first region of the lower redistribution wiring layer, a molding member covering the semiconductor chip on the lower redistribution wiring layer, a plurality of vertical conductive structures penetrating the molding member on the second region of the lower redistribution wiring layer, electrically connected to the first redistribution wirings, and including first conductive pillars and second conductive pillars stacked on the first conductive pillars respectively, and an upper redistribution wiring layer disposed on the molding member and having second redistribution wirings electrically connected to the plurality of vertical conductive structures. Each of the first conductive pillars has a first length and each of the second conductive pillars has a second length greater than the first length.

公开(公告)号：US20240213223A1

公开(公告)日：2024-06-27

申请号：US18516367

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemok JUNG ,  Dowan KIM ,  Sungkeun PARK ,  Jongho PARK ,  Juil CHOI

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/08056 ,  H01L2224/08245 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06544 ,  H01L2924/181

Abstract: A semiconductor package includes a first redistribution wiring layer having a first region and a second region surrounding the first region, a semiconductor chip disposed on the first region of the first redistribution wiring layer, a sealing member covering the semiconductor chip on the first redistribution wiring layer, vertical conductive wires penetrating the sealing member on the second region of the first redistribution wiring layer, a second redistribution wiring layer disposed on the sealing member and including second redistribution wirings electrically connected to the vertical conductive wires, and bonding pads provided on an upper surface of the first redistribution wiring layer or a lower surface of the second redistribution wiring layer, each bonding pad having a concavo-convex pattern on an upper surface of the bonding pad. The vertical conductive wires are bonded to the concavo-convex patterns of the bonding pads, respectively.

公开(公告)号：US20240079394A1

公开(公告)日：2024-03-07

申请号：US18366054

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juil CHOI ,  Jongho PARK ,  Sanghyuck OH ,  Jaeyoung LEE ,  Jaemok JUNG ,  Hongseo HEO

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H10B80/00 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package may include a first redistribution structure, a first semiconductor chip on the first redistribution structure, a first molding layer covering the first semiconductor chip, first connection structures on the first redistribution structure and extending in a vertical direction while passing through the first molding layer, a second redistribution structure on the first semiconductor chip, a second semiconductor chip on the second redistribution structure, and a metal layer on the second semiconductor chip. The metal layer may be in contact with an upper surface of the second semiconductor chip.

公开(公告)号：US20230060115A1

公开(公告)日：2023-02-23

申请号：US17723552

申请日：2022-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sechul PARK ,  Unbyoung KANG ,  Heewon KIM ,  Jongho PARK ,  Hyojin YUN ,  Juil CHOI

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip on a base chip, a second semiconductor chip on the first semiconductor chip in a first direction, each of the first and second semiconductor chips including a TSV and being electrically connected to each other via the TSV, dam structures on the base chip and surrounding a periphery of the first semiconductor chip, a first adhesive film between the base chip and the first semiconductor chip, a portion of the first adhesive film filling a space between the first semiconductor chip and the dam structures, a second adhesive film between the first semiconductor chip and the second semiconductor chip, a portion of the second adhesive film overlapping the dam structures in the first direction, and an encapsulant encapsulating a portion of each of the dam structures, the first semiconductor chip, and the second semiconductor chip.

公开(公告)号：US20210335688A1

公开(公告)日：2021-10-28

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji SONG ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.