公开(公告)号：US09053774B2

公开(公告)日：2015-06-09

申请号：US14066193

申请日：2013-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Ho-Sung Song

IPC: G11C7/00 ,  G11C8/18 ,  H03K5/156 ,  G11C29/02

CPC classification number: G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03K5/1565

Abstract: A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal.

Abstract translation: 占空比校正器包括感测单元，衬垫单元，保险丝单元和驱动单元。 感测单元基于感测到的输出信号的占空比来产生至少一个感测信号。 垫单元基于至少一个感测信号输出至少一个判定信号。 熔丝单元基于至少一个接收的熔丝控制信号产生占空比控制信号。 驱动单元根据占空比控制信号来调整输入信号的占空比，生成输出信号。 驱动器单元通过基于占空比控制信号调整输入信号的上拉强度或下拉强度来调节输入信号的占空比。

公开(公告)号：US20130214843A1

公开(公告)日：2013-08-22

申请号：US13717931

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Soo Ha ,  Ho-Seok Seol ,  Woo-Jin Lee

IPC: H03K19/0185

CPC classification number: H03K19/018514

Abstract: A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.

Abstract translation: 提供了缓冲电路，其对于占空比失真不敏感，而与操作环境的变化无关。 缓冲电路包括电流模式逻辑缓冲器和差分到单端转换器。 差分到单端转换器接收第一和第二差分输出信号以产生单端输出信号，并且被配置为使得差分到单端转换器的内部控制节点以负反馈方式被控制 保持单端输出信号的恒定占空比，而不管操作环境的变化。 根据一些实施例，减少或最小化由于诸如处理，电压，温度等的操作环境的改变引起的单端输出信号的占空比失真，从而提高缓冲电路的性能和操作可靠性 改进了

公开(公告)号：US09264039B2

公开(公告)日：2016-02-16

申请号：US14202323

申请日：2014-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

CPC classification number: H03K19/0005

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract translation: 片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。 校准单元生成一个上拉代码和一个下拉代码。 偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。 加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

公开(公告)号：US09171605B1

公开(公告)日：2015-10-27

申请号：US14103794

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sik Kim ,  Won-Il Bae ,  Myeong-O Kim ,  Min-Soo Kim ,  Ho-Seok Seol ,  Min-Sang Park ,  Kyo-Min Sohn ,  Chi-Hwan Lee ,  Sang-Joon Hwang

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F12/1018 ,  G11C7/00 ,  G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/408

Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Abstract translation: 提供了使用n位地址来检测半导体器件的集中地址的方法。 该方法包括：对于k组中的每一组，将n位地址划分为k个组，其中n和k中的每一个是等于或大于2的整数，检测对应于该组的一个或多个集中子地址，以及 通过组合用于k个组的一个或多个集中子地址来生成至少一个集中地址。

公开(公告)号：US10468092B2

公开(公告)日：2019-11-05

申请号：US16288626

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-ho Hyun ,  Kyo-min Sohn ,  Je-min Ryu ,  Ho-Seok Seol

IPC: G11C11/408 ,  G11C11/406 ,  G11C11/4093

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

公开(公告)号：US20190198087A1

公开(公告)日：2019-06-27

申请号：US16288626

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-ho HYUN ,  Kyo-min Sohn ,  Je-min Ryu ,  Ho-Seok Seol

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2211/4061

Abstract: A memory device includes a memory cell array that includes a plurality of memory cell rows; and a refresh address generator configured to store flags respectively corresponding to the plurality of memory cell rows, generate refresh row addresses respectively corresponding to the plurality of memory cell rows by performing a count operation, and according to the flags, change a refresh period of the plurality of memory cell rows.

公开(公告)号：US08742801B2

公开(公告)日：2014-06-03

申请号：US13717931

申请日：2012-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Soo Ha ,  Ho-Seok Seol ,  Woo-Jin Lee

IPC: H03K3/00

CPC classification number: H03K19/018514

Abstract: A buffer circuit is provided which is insensitive to a duty distortion regardless of the change of operation environment. The buffer circuit includes a current mode logic buffer and a differential-to-single-ended converter. The differential-to-single-ended converter receives first and second differential output signals to generate a single ended output signal and is configured so that an internal control node of the differential-to-single-ended converter is controlled in a negative feedback method to maintain a constant duty ratio of the single ended output signal regardless of the change of operation environment. According to some embodiments, a duty distortion of the single ended output signal due to the change of operation environment such as a process, a voltage, a temperature, etc. is reduced or minimized and thereby performance of the buffer circuit is improved and operation reliability is improved.

Abstract translation: 提供了缓冲电路，其对于占空比失真不敏感，而与操作环境的变化无关。 缓冲电路包括电流模式逻辑缓冲器和差分到单端转换器。 差分到单端转换器接收第一和第二差分输出信号以产生单端输出信号，并且被配置为使得差分到单端转换器的内部控制节点以负反馈方式被控制 保持单端输出信号的恒定占空比，而不管操作环境的变化。 根据一些实施例，减少或最小化由于诸如处理，电压，温度等的操作环境的改变引起的单端输出信号的占空比失真，从而提高缓冲电路的性能和操作可靠性 改进了