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公开(公告)号：US12072374B2
公开(公告)日：2024-08-27
申请号：US17540745
申请日：2021-12-02
发明人： Jihoon Chang , Yeonjin Lee , Minjung Choi , Jimin Choi
IPC分类号： G01R31/28 , H01L23/00 , H01L23/522 , H01L23/528
CPC分类号： G01R31/2884 , H01L23/5226 , H01L23/528 , H01L24/05 , H01L24/06 , H01L2224/05097 , H01L2224/06515
摘要： A detection pad structure in a semiconductor device may include a lower wiring on a substrate, an upper wiring on the lower wiring, and a first pad pattern on the upper wiring. The upper wiring may be connected to the lower wiring and include metal patterns and via contacts on the metal patterns that are stacked in a plurality of layers. The first pad pattern may be connected to the upper wiring. A semiconductor device may include an actual upper wiring including actual metal patterns and actual via contacts stacked in a plurality of layers. At least one of the metal patterns of each layer in the upper wiring may have a minimum line width and a minimum space of the metal patterns of each layer in the actual upper wiring. Metal patterns and via contacts of each layer in the upper wiring may be regularly and repeatedly arranged.
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公开(公告)号：US11049827B2
公开(公告)日：2021-06-29
申请号：US16795658
申请日：2020-02-20
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US11817408B2
公开(公告)日：2023-11-14
申请号：US18093880
申请日：2023-01-06
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC分类号： H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US20210057328A1
公开(公告)日：2021-02-25
申请号：US16848246
申请日：2020-04-14
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/522 , H01L23/31 , H01L23/48 , H01L23/00 , H01L23/528
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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公开(公告)号：US12080663B2
公开(公告)日：2024-09-03
申请号：US18377530
申请日：2023-10-06
发明人： Minjung Choi , Sooho Shin , Yeonjin Lee , Junghoon Han
CPC分类号： H01L24/05 , H01L21/561 , H01L24/13 , H01L24/73 , H01L24/96 , H01L2224/0401 , H01L2224/12105 , H01L2224/13099 , H01L2224/81801 , H01L2924/1304 , H01L2924/18162
摘要： A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.
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公开(公告)号：US11776894B2
公开(公告)日：2023-10-03
申请号：US16848246
申请日：2020-04-14
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/48 , H01L23/485 , H01L23/522 , H01L23/532 , H01L23/00 , H01L23/31 , H01L21/768 , H01L25/065 , H01L21/76 , H01L23/525 , H01L21/78 , H01L21/82 , H01L23/528 , H01L21/56
CPC分类号： H01L23/5222 , H01L21/561 , H01L21/76832 , H01L21/78 , H01L21/82 , H01L23/3185 , H01L23/481 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L23/53295 , H01L24/05 , H01L23/562 , H01L2224/024 , H01L2224/0237
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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公开(公告)号：US20230230915A1
公开(公告)日：2023-07-20
申请号：US18127342
申请日：2023-03-28
发明人： Yeonjin Lee , Junyong Noh , Minjung Choi , Junghoon Han , Yunrae Cho
IPC分类号： H01L23/522 , H01L23/31 , H01L23/00 , H01L23/528 , H01L23/48 , H01L23/532 , H01L21/768 , H01L23/485 , H01L21/82 , H01L21/56 , H01L21/78
CPC分类号： H01L23/5222 , H01L23/3185 , H01L24/05 , H01L23/5283 , H01L23/481 , H01L23/53295 , H01L21/76832 , H01L23/485 , H01L23/5226 , H01L21/82 , H01L21/561 , H01L21/78 , H01L23/562 , H01L2224/0237 , H01L2224/024
摘要： A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.
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公开(公告)号：US11670559B2
公开(公告)日：2023-06-06
申请号：US17206295
申请日：2021-03-19
发明人： Minjung Choi , Jung-Hoon Han , Jiho Kim , Young-Yong Byun , Yeonjin Lee , Jihoon Chang
CPC分类号： H01L23/3171 , H01L23/3192 , H01L23/528 , H01L21/78 , H01L23/291 , H01L23/296 , H01L23/585 , H01L24/05 , H01L2224/0219 , H01L2224/0221 , H01L2224/02181 , H01L2224/05541 , H01L2224/05553
摘要： A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.
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9.发明授权公开(公告)号：US11342235B2
公开(公告)日：2022-05-24
申请号：US16898943
申请日：2020-06-11
发明人： Minjung Choi , Junyong Noh , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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10.发明授权公开(公告)号：US11756843B2
公开(公告)日：2023-09-12
申请号：US17706401
申请日：2022-03-28
发明人： Minjung Choi , Junyong Noh , Yeonjin Lee , Junghoon Han
摘要： A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.
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