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公开(公告)号:US08980731B2
公开(公告)日:2015-03-17
申请号:US13724632
申请日:2012-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Ho Kim , Sunghae Lee , Hanvit Yang , Dongwoo Kim , Chaeho Kim , Daehyun Jang , Ju-Eun Kim , Yong-Hoon Son , Sangryol Yang , Myoungbum Lee , Kihyun Hwang
IPC: H01L21/04 , H01L21/82 , H01L21/336 , H01L21/3205 , H01L29/76 , H01L29/792 , H01L27/115 , H01L29/66
CPC classification number: H01L21/04 , H01L27/11582 , H01L29/66833 , H01L29/7926
Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.
Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层,以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外,所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。
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公开(公告)号:US09893082B2
公开(公告)日:2018-02-13
申请号:US15250091
申请日:2016-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chaeho Kim , Sangryol Yang , Woong Lee , SeungHyun Lim
IPC: H01L27/115 , H01L29/423 , H01L27/11582 , H01L27/11573 , H01L29/51 , H01L27/11575 , H01L27/11565
CPC classification number: H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/42348 , H01L29/513
Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.
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公开(公告)号:US09293336B2
公开(公告)日:2016-03-22
申请号:US14258107
申请日:2014-04-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangryol Yang , Soonwook Jung , Kyoungseob Kim , Youngsub You , Byunghong Chung , Hanmei Choi
IPC: H01L29/40 , H01L21/283 , H01L21/768
CPC classification number: H01L21/283 , H01L21/76805 , H01L29/401
Abstract: A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact.
Abstract translation: 半导体器件包括在衬底上的存储节点接触和存储节点接触件上的下电极,下电极的下侧壁由与存储节点接触件相同的材料的接触残余物覆盖。
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公开(公告)号:US09466612B2
公开(公告)日:2016-10-11
申请号:US14985730
申请日:2015-12-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
IPC: H01L29/76 , H01L27/115 , H01L29/792 , H01L21/02 , H01L21/306 , H01L21/324
CPC classification number: H01L27/11582 , H01L21/02675 , H01L21/30604 , H01L21/324 , H01L27/11551 , H01L27/11578 , H01L29/7926
Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.
Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中,该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中,该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外,该方法可以包括在第二通过区域中形成第二半导体层。
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5.
公开(公告)号:US20160118400A1
公开(公告)日:2016-04-28
申请号:US14985730
申请日:2015-12-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
IPC: H01L27/115 , H01L21/306 , H01L21/324
CPC classification number: H01L27/11582 , H01L21/02675 , H01L21/30604 , H01L21/324 , H01L27/11551 , H01L27/11578 , H01L29/7926
Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.
Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中,该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中,该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外,该方法可以包括在第二通过区域中形成第二半导体层。
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公开(公告)号:US09257441B2
公开(公告)日:2016-02-09
申请号:US14082657
申请日:2013-11-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Ho Kim , Daehyun Jang , Myoungbum Lee , Kihyun Hwang , Sangryol Yang , Yong-Hoon Son , Ju-Eun Kim , Sunghae Lee , Dongwoo Kim , JinGyun Kim
IPC: H01L29/76 , H01L27/115 , H01L29/792 , H01L21/02
CPC classification number: H01L27/11582 , H01L21/02675 , H01L21/30604 , H01L21/324 , H01L27/11551 , H01L27/11578 , H01L29/7926
Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.
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