公开(公告)号：US20200303266A1

公开(公告)日：2020-09-24

申请号：US16711771

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongrak JEONG ,  Seungmo KANG

IPC: H01L21/66 ,  H01L21/265 ,  G06N3/08 ,  G06N3/04 ,  C23C14/48 ,  C23C14/54

Abstract: An ion depth profile control method includes performing reinforcement learning, whereby a similarity between an ion depth profile and a box profile is output as a reward when the similarity is equal to or greater than a set criterion, the ion depth profile being an ion concentration according to a wafer depth in an ion implantation process, and the box profile being a target profile, obtaining at least one process condition of the ion implantation process as a result of the reinforcement learning, and generating a process recipe regarding the at least one process condition.

公开(公告)号：US20230387207A1

公开(公告)日：2023-11-30

申请号：US18155532

申请日：2023-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juri LEE ,  Taegon KIM ,  Seungmo KANG ,  Sihyung LEE

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/775 ,  H01L21/265

CPC classification number: H01L29/0847 ,  H01L29/16 ,  H01L29/41733 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L21/26506 ,  H01L29/0673

Abstract: An integrated circuit (IC) device includes a fin-type active region extending long in a first lateral direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region, and a source/drain region adjacent to the gate line on the fin-type active region, the source/drain region. The source/drain region includes a lower source/drain region and an upper source/drain region. The lower source/drain region includes at least one silicon isotope selected from silicon isotopes of 28Si, 29Si, and 30Si, and the upper source/drain region includes a 28Si element at a content higher than a content of the 28Si element in the lower source/drain region.

公开(公告)号：US20170062367A1

公开(公告)日：2017-03-02

申请号：US15222114

申请日：2016-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： AHYUN JO ,  Seungmo KANG ,  Yooncheol BANG ,  Seokwoo HONG

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66 ,  H01L23/31

CPC classification number: H01L24/09 ,  H01L22/14 ,  H01L22/32 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/33 ,  H01L25/0657 ,  H01L2224/02313 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03622 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/06151 ,  H01L2224/06155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

Abstract translation: 公开了包括其的半导体芯片和/或半导体封装。 半导体芯片可以包括在基板上的集成电路，与集成电路电连接的中心焊盘，在中心焊盘上的下绝缘结构，并具有暴露中心焊盘的接触孔，下绝缘结构包括多个下绝缘体 依次堆叠在基板上的导电图案，包括接触部分，焊盘部分，导电线部分，填充接触孔的接触部分，包括测试区域和接合区域的焊盘部分的导电图案， 下绝缘结构并将接触部分连接到焊盘部分，以及在导电图案上的上绝缘结构，并具有暴露焊盘部分的第一开口，以及包括上绝缘层和聚合物层的上绝缘结构。