公开(公告)号：US20240188293A1

公开(公告)日：2024-06-06

申请号：US18229296

申请日：2023-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sam Ki KIM ,  Nam Bin KIM ,  Ji Woong KIM ,  Tae Hun KIM ,  Ki Bong MOON ,  Sae Rom LEE ,  Sung-Bok LEE ,  Jun Hee LIM ,  Nag Yong CHOI ,  Sun Gyung HWANG

IPC: H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B43/40

Abstract: A semiconductor memory device including a substrate; a mold structure including gate electrodes and mold insulating layers stacked in a stair shape, channel structures on the substrate, intersecting the gate electrodes, and passing through the mold structure; cell contacts connected to the gate electrodes; a first interlayer insulating layer on the mold structure and covering the channel structures and cell contacts; first metal patterns connected to the channel structures, an upper surface of the first metal patterns being coplanar with an upper surface of the first interlayer insulating layer; second metal patterns connected to the cell contacts, an upper surface of the second metal patterns being coplanar with the upper surface of the first metal patterns; a first blocking layer along the upper surface of the first interlayer insulating layer, the first metal patterns, and the second metal patterns; and a first dummy vias passing through the first blocking layer.

公开(公告)号：US20250078929A1

公开(公告)日：2025-03-06

申请号：US18679809

申请日：2024-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kibong MOON ,  Suck-Soo KIM ,  Tae Hun KIM ,  Hyoje BANG ,  Seung Jae BAIK ,  Sung-Bok LEE ,  Jaeduk LEE ,  Junhee LIM

IPC: G11C16/04 ,  G11C5/06 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a substrate, a plurality of cell strings perpendicular to an upper surface of the substrate, and a bit line connected to at least six of the cell strings. Each of the cell strings may include a plurality of memory cells connected in series to each other in a direction perpendicular to the upper surface of the substrate, first to fourth ground selection transistors connected in series to each other between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and the bit line. A first one of the first to fourth selection ground selection transistors may have a first threshold voltage distribution, and a second one of the first to fourth ground selection transistors may have a second threshold voltage distribution. The second threshold voltage distribution may be different from the first threshold voltage distribution.

公开(公告)号：US20190129655A1

公开(公告)日：2019-05-02

申请号：US16023706

申请日：2018-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raeyoung LEE ,  Hyunjung KIM ,  Sung-Bok LEE ,  Soyeong GWAK ,  Sang-wan NAM

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G06F11/10 ,  G11C29/52

Abstract: A method of operating a memory controller, the memory controller configured to control a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks. The method including detecting an invalid block among the plurality of memory blocks; determining an invalid pattern based on a state of the invalid block; and performing an operation on the invalid block such that the invalid block has the invalid pattern.