公开(公告)号：US20230259300A1

公开(公告)日：2023-08-17

申请号：US17674543

申请日：2022-02-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Aaron Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

公开(公告)号：US10978156B2

公开(公告)日：2021-04-13

申请号：US16024002

申请日：2018-06-29

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C8/12 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US20170243638A1

公开(公告)日：2017-08-24

申请号：US15588968

申请日：2017-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

公开(公告)号：US11342028B2

公开(公告)日：2022-05-24

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US09899077B2

公开(公告)日：2018-02-20

申请号：US15588968

申请日：2017-05-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

公开(公告)号：US09760303B2

公开(公告)日：2017-09-12

申请号：US14869686

申请日：2015-09-29

Applicant: SanDisk Technologies LLC

Inventor： Dennis S. Ea ,  Ivan Baran ,  Aaron Lee ,  Mrinal Kochar ,  Mikhail Palityka ,  Yew Yin Ng ,  Abhijeet Bhalerao

IPC: G06F12/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C29/00 ,  G06F12/02 ,  G06F11/10

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0667 ,  G06F3/0679 ,  G06F11/1048 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C11/5621 ,  G11C16/0483 ,  G11C29/76 ,  G11C29/765 ,  G11C29/808 ,  G11C29/82 ,  G11C29/88

Abstract: Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

公开(公告)号：US09653154B2

公开(公告)日：2017-05-16

申请号：US14860086

申请日：2015-09-21

Applicant: SanDisk Technologies LLC

Inventor： Cynthia Hua-Ling Hsu ,  Aaron Lee ,  Abhijeet Manohar ,  Deepanshu Dutta

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/3459

Abstract: Techniques are presented to determine whether a multi-state memory device suffers has a write operation aborted prior to its completion. In an example where all the word lines of a memory block is first programmed to an intermediate level (such as 2 bits per cells) before then being fully written (such as 4 bits per cell), after determining that intermediate programming pass completed, the block is searched using the read level for the highest multi-state to find the last fully programmed word line, after which the next word line is checked with the lowest state's read level to determine whether the full programming had begun on this word line. In an example where each word line is fully written before beginning the next word line of the block, after determining the first erased word line, the preceding word line is checked as the highest state to see if programming completed and, if not, checked at the lowest read level to see if programming began.

公开(公告)号：US11966621B2

公开(公告)日：2024-04-23

申请号：US17674543

申请日：2022-02-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  Aaron Lee

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7203

Abstract: Technology is disclosed for a non-volatile memory system that decouples dataload from program execution. A memory controller transfers data for a program operation and issues a first type of program execution command. When in a coupled mode, the die programs the data in response to the first type of program execution command. When in a decoupled mode, rather than program the data into non-volatile memory cells the die enters a wait state. Optionally, the memory controller can instruct another die to execute a memory operation while the first die is in the wait state. In response to receiving a second type of program execution command from the memory controller when in the wait state, the first die will program the data into non-volatile memory cells. The memory controller may issue the second type of program execution command in response to determining that sufficient power resources (or thermal budget) exist.

公开(公告)号：US20210233589A1

公开(公告)日：2021-07-29

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US11004535B1

公开(公告)日：2021-05-11

申请号：US16717494

申请日：2019-12-17

Applicant: SanDisk Technologies LLC

Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li ,  Aaron Lee

IPC: G11C29/00 ,  G11C29/02 ,  G11C7/10 ,  G11C11/4094 ,  G11C11/408

Abstract: Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.