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1.发明公开公开(公告)号：US20240237355A9
公开(公告)日：2024-07-11
申请号：US18350524
申请日：2023-07-11
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Monica TITUS , Raghuveer S. MAKALA , Rahul SHARANGPANI , Senaka KANAKAMEDALA
IPC: H10B43/35 , G11C16/04 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27
CPC classification number: H10B43/35 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27
Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.
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2.发明公开公开(公告)号：US20240138151A1
公开(公告)日：2024-04-25
申请号：US18350524
申请日：2023-07-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Monica TITUS , Raghuveer S. MAKALA , Rahul SHARANGPANI , Senaka KANAKAMEDALA
IPC: H10B43/35 , G11C16/04 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27
CPC classification number: H10B43/35 , G11C16/0483 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27
Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.
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3.发明公开公开(公告)号：US20240074200A1
公开(公告)日：2024-02-29
申请号：US17821677
申请日：2022-08-23
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Senaka KANAKAMEDALA , Raghuveer S. MAKALA
IPC: H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11582
CPC classification number: H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/11582
Abstract: A first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers is formed over a substrate. A first-tier memory opening is formed, and is filled with a first-tier sacrificial memory opening fill structure. A second-tier alternating stack of second-tier insulating layers and second-tier sacrificial material layers is formed. An etch mask layer is formed, and a second-tier memory opening is formed through the second-tier alternating stack. An etch mask removal process is performed which collaterally removes a top portion of the first-tier sacrificial memory opening fill structure. A sacrificial pillar structure is formed by performing a selective material deposition process. An inter-tier memory opening is formed by removing the first-tier sacrificial memory opening fill structure and at least a central portion of the sacrificial pillar structure. A memory opening fill structure is formed, and the sacrificial material layers are replaced with electrically conductive layers.
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4.发明公开公开(公告)号：US20230178425A1
公开(公告)日：2023-06-08
申请号：US18151662
申请日：2023-01-09
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Roshan Jayakhar TIRUKKONDA , Bing ZHOU , Rahul SHARANGPANI , Raghuveer S. MAKALA , Senaka KANAKAMEDALA , Adarsh RAJASHEKHAR
IPC: H01L21/768 , H01L21/306
CPC classification number: H01L21/76831 , H01L21/30608
Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.
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5.发明公开公开(公告)号：US20240349501A1
公开(公告)日：2024-10-17
申请号：US18363486
申请日：2023-08-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Rahul SHARANGPANI , Raghuveer S. MAKALA , Adarsh RAJASHEKHAR , Bing ZHOU , Senaka KANAKAMEDALA
CPC classification number: H10B43/27 , G11C16/0483 , H10B43/10 , H10B43/35
Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20240349500A1
公开(公告)日：2024-10-17
申请号：US18363460
申请日：2023-08-01
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Raghuveer S. MAKALA , Senaka KANAKAMEDALA , Rahul SHARANGPANI , Adarsh RAJASHEKHAR
IPC: H10B43/27 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/18 , H10B41/27 , H10B41/35 , H10B43/35 , H10B80/00
CPC classification number: H10B43/27 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B41/27 , H10B41/35 , H10B43/35 , H10B80/00 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack and a memory opening fill structure located in the memory opening. A Group IV-containing material portion is formed by selective deposition on an end portion of the vertical semiconductor channel. Alternatively, a backside semiconductor cap structure can be formed directly on a bottom surface of the vertical semiconductor channel by selective or non-selective deposition of a semiconductor material.
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公开(公告)号：US20240237346A1
公开(公告)日：2024-07-11
申请号：US18355888
申请日：2023-07-20
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Rahul SHARANGPANI , Raghuveer S. MAKALA , Adarsh RAJASHEKHAR , Fei ZHOU , Bing ZHOU , Senaka KANAKAMEDALA , Roshan Jayakhar TIRUKKONDA , Kartik SONDHI
IPC: H10B43/27 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35
CPC classification number: H10B43/27 , H01L23/5226 , H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/35
Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers including a first insulating material and sacrificial material layers including a first sacrificial material over a substrate, forming a memory opening through the alternating stack, performing a first selective material deposition process that selectively grows a second sacrificial material from physically exposed surfaces of the sacrificial material layers to form a vertical stack of sacrificial material portions; forming a memory opening fill structure in the memory opening, where the memory opening fill structure includes a vertical stack of memory elements and a vertical semiconductor channel, and replacing a combination of the vertical stack of sacrificial material portions and the sacrificial material layers with electrically conductive layers.
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8.发明公开公开(公告)号：US20240237343A9
公开(公告)日：2024-07-11
申请号：US18350552
申请日：2023-07-11
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Monica TITUS , Raghuveer S. MAKALA , Rahul SHARANGPANI , Senaka KANAKAMEDALA
Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.
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9.发明公开公开(公告)号：US20240138149A1
公开(公告)日：2024-04-25
申请号：US18350552
申请日：2023-07-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Bing ZHOU , Monica TITUS , Raghuveer S. MAKALA , Rahul SHARANGPANI , Senaka KANAKAMEDALA
Abstract: A etch stop structure is formed a sacrificial memory opening fill structure formed within a first-tier memory opening vertically extending through a first-tier alternating stack of first insulating layers and first spacer material layers. The etch stop structure may include a conductive etch stop plate that is formed over a sacrificial memory opening fill material portion inside the first-tier memory opening, or may include a semiconductor plug which is selectively grown from sidewalls of an etch stop semiconductor material layer that is formed over the first-tier alternating stack. A second-tier alternating stack of second insulating layers and second spacer material layers is formed over the first-tier alternating stack and the etch stop structure.
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10.发明公开公开(公告)号：US20240237350A1
公开(公告)日：2024-07-11
申请号：US18534283
申请日：2023-12-08
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Kartik SONDHI , Roshan Jayakhar TIRUKKONDA , Bing ZHOU , Senaka KANAKAMEDALA
Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements and a vertical semiconductor channel, and a vertical stack of insulating spacers located at levels of the insulating layers between the memory opening fill structure and the insulating layers. The insulating spacers have different thicknesses such that the thicknesses of the insulating spacers increase with an upward vertical distance from a horizontal plane including a top surface of the substrate.
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