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公开(公告)号:US10379940B2
公开(公告)日:2019-08-13
申请号:US15372485
申请日:2016-12-08
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Omer Fainzilber , Ariel Navon , Alexander Bazarsky , David Gur , Stella Achtenberg
IPC: G06F11/10
Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.
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公开(公告)号:US10158380B2
公开(公告)日:2018-12-18
申请号:US15371167
申请日:2016-12-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Eran Sharon , Alexander Bazarsky , Idan Goldenberg , Stella Achtenberg , Omer Fainzilber , Ran Zamir
Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.
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公开(公告)号:US10116333B2
公开(公告)日:2018-10-30
申请号:US15223531
申请日:2016-07-29
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Ran Zamir , Alexander Bazarsky , Stella Achtenberg , Omer Fainzilber , Eran Sharon
IPC: H03M13/11 , G11C16/08 , G06F11/10 , H03M13/00 , G11C16/16 , G11C16/26 , G11C16/10 , G11C11/56 , G11C16/04
Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.
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公开(公告)号:US10110249B2
公开(公告)日:2018-10-23
申请号:US15244444
申请日:2016-08-23
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Xinmiao Zhang , Alexander Bazarsky , Ran Zamir , Eran Sharon , Idan Alrod , Omer Fainzilber , Sanel Alterman
Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.
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公开(公告)号:US10250281B2
公开(公告)日:2019-04-02
申请号:US15395185
申请日:2016-12-30
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Stella Achtenberg , Omer Fainzilber , Ariel Navon , Alexander Bazarsky , Eran Sharon
Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.
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公开(公告)号:US09947401B1
公开(公告)日:2018-04-17
申请号:US15388154
申请日:2016-12-22
Applicant: SanDisk Technologies LLC
Inventor: Ariel Navon , Tz-Yi Liu , Eran Sharon , Alexander Bazarsky , Judah Hahn , Alon Eyal , Omer Fainzilber
CPC classification number: G11C13/0069 , G06F11/0727 , G06F11/076 , G06F11/0793 , G06F11/1068 , G06F11/3034 , G06F11/3062 , G11C13/0023 , G11C13/0038 , G11C29/52 , G11C2013/0078
Abstract: Technology is described for keeping current (e.g., peak power supply current or ICC) in a non-volatile memory system within a target while maintaining high throughput. Programming conditions are adaptively changed at the sub-codeword level in order to keep power supply current of the memory system within a target. In one embodiment, a chunk of data that corresponds to a sub-codeword is written while consuming lower than normal programming current in order to keep power supply current within a target. The relatively low programming current may increase the expected raw BER. However, other portions of the codeword can be written with a higher than normal programming current, which results in a lower expected bit raw error rate for the memory cells that store that portion.
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