公开(公告)号：US10567001B2

公开(公告)日：2020-02-18

申请号：US16049069

申请日：2018-07-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Idan Goldenberg ,  Ishai Ilani ,  Alexander Bazarsky ,  Rami Rom

IPC: H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  G06F11/10 ,  H03M13/35

Abstract: In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

公开(公告)号：US10474525B2

公开(公告)日：2019-11-12

申请号：US14823747

申请日：2015-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Ariel Navon ,  Idan Alrod ,  Alexander Bazarsky

IPC: G11C11/56 ,  G06F11/10 ,  G11C16/28 ,  G06F3/06 ,  G11C29/52

Abstract: A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.

公开(公告)号：US20190163367A1

公开(公告)日：2019-05-30

申请号：US16262125

申请日：2019-01-30

Applicant: SanDisk Technologies LLC

Inventor： Alexander Bazarsky ,  Grishma Shah ,  Idan Alrod ,  Eran Sharon

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.

公开(公告)号：US10236909B2

公开(公告)日：2019-03-19

申请号：US15475666

申请日：2017-03-31

Applicant: SanDisk Technologies LLC

Inventor： Rami Rom ,  Idan Goldenberg ,  Alexander Bazarsky ,  Eran Sharon ,  Ran Zamir ,  Idan Alrod ,  Stella Achtenberg

IPC: H03M13/11 ,  H03M13/00 ,  G06F3/06

Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.

公开(公告)号：US10158380B2

公开(公告)日：2018-12-18

申请号：US15371167

申请日：2016-12-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Eran Sharon ,  Alexander Bazarsky ,  Idan Goldenberg ,  Stella Achtenberg ,  Omer Fainzilber ,  Ran Zamir

IPC: G11C29/00 ,  H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  H03M13/29

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a first count of bits of a representation of data that are estimated to be erroneous and a second count of bits of the representation of data that have high estimated reliability and are estimated to be erroneous. The controller is further configured to modify at least one read parameter or at least one decode parameter based on the first count and the second count.

公开(公告)号：US10116333B2

公开(公告)日：2018-10-30

申请号：US15223531

申请日：2016-07-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ran Zamir ,  Alexander Bazarsky ,  Stella Achtenberg ,  Omer Fainzilber ,  Eran Sharon

IPC: H03M13/11 ,  G11C16/08 ,  G06F11/10 ,  H03M13/00 ,  G11C16/16 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: A device includes a memory configured to store syndromes, a first data processing unit coupled to the memory, and a second data processing unit coupled to the memory. The first data processing unit is configured to process a first value corresponding to a first symbol of data to be decoded. The second data processing unit is configured to process a second value corresponding to a second symbol of the data. Syndrome aggregation circuitry is coupled to the first data processing unit and to the second data processing unit. The syndrome aggregation circuitry is configured to combine syndrome change decisions of the first data processing unit and the second data processing unit.

公开(公告)号：US10110249B2

公开(公告)日：2018-10-23

申请号：US15244444

申请日：2016-08-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xinmiao Zhang ,  Alexander Bazarsky ,  Ran Zamir ,  Eran Sharon ,  Idan Alrod ,  Omer Fainzilber ,  Sanel Alterman

IPC: H03M13/00 ,  H03M13/11 ,  G06F11/10 ,  G11C29/52

Abstract: In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

公开(公告)号：US20180089024A1

公开(公告)日：2018-03-29

申请号：US15274037

申请日：2016-09-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Judah Gamliel Hahn ,  Gadi Vishne ,  Joshua Lehmann ,  Alexander Bazarsky ,  Ariel Navon

IPC: G06F11/10 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H04L1/0015 ,  H04L1/0017 ,  H04L1/0025 ,  H04L1/0026 ,  H04L1/004 ,  H04L29/06523 ,  H04L41/5022 ,  H04L41/5025

Abstract: A non-volatile memory system receives a request to read data. That request includes a quality of service indication. The memory system performs a read process that satisfies the quality of service indication and identifies a set of data with errors. The memory system returns the set of data with errors in response to the request.

公开(公告)号：US11670380B2

公开(公告)日：2023-06-06

申请号：US17114256

申请日：2020-12-07

Applicant: SanDisk Technologies LLC

Inventor： Eran Sharon ,  Idan Alrod ,  Alexander Bazarsky

IPC: G11C16/04 ,  G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L23/00 ,  H01L27/11582 ,  H01L25/065

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  H01L24/08 ,  H01L25/0657 ,  H01L27/11582 ,  H01L2224/08145 ,  H01L2225/06506 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

公开(公告)号：US20220180940A1

公开(公告)日：2022-06-09

申请号：US17114256

申请日：2020-12-07

Applicant: SanDisk Technologies LLC

Inventor： Eran Sharon ,  Idan Alrod ,  Alexander Bazarsky

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11582

Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.