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公开(公告)号：US10250281B2
公开(公告)日：2019-04-02
申请号：US15395185
申请日：2016-12-30
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Stella Achtenberg , Omer Fainzilber , Ariel Navon , Alexander Bazarsky , Eran Sharon
Abstract: A device includes a non-volatile memory, a traffic analyzer, and a parameter adjuster. The traffic analyzer is configured to generate a traffic type indicator based on one or more read requests from an access device to access data at the non-volatile memory. The traffic type indicator has a first value responsive to the one or more read requests corresponding to a first traffic type and has a second value responsive to the one or more read requests corresponding to a second traffic type. The parameter adjuster is configured to designate one or more decode parameter values based on the traffic type indicator.
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公开(公告)号：US10230395B2
公开(公告)日：2019-03-12
申请号：US15475638
申请日：2017-03-31
Applicant: SanDisk Technologies LLC
Inventor： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US20180287636A1
公开(公告)日：2018-10-04
申请号：US15475638
申请日：2017-03-31
Applicant: SanDisk Technologies LLC
Inventor： Rami Rom , ldan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , ldan Alrod , Stella Achtenberg
CPC classification number: H03M13/1125 , G06F3/0619 , G06F3/0655 , G06F3/0688 , H03M13/6566
Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10367528B2
公开(公告)日：2019-07-30
申请号：US15179069
申请日：2016-06-10
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Idan Goldenberg , Alexander Bazarsky , Stella Achtenberg , Ishai Ilani , Eran Sharon
Abstract: In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.
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公开(公告)号：US20180287632A1
公开(公告)日：2018-10-04
申请号：US15475666
申请日：2017-03-31
Applicant: SanDisk Technologies LLC
Inventor： Rami Rom , ldan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , ldan Alrod , Stella Achtenberg
CPC classification number: H03M13/11 , G06F3/0619 , G06F3/0655 , G06F3/0688 , H03M13/1125 , H03M13/6566
Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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Patent Agency Ranking
公开(公告)号：US10379940B2
公开(公告)日：2019-08-13
申请号：US15372485
申请日：2016-12-08
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Omer Fainzilber , Ariel Navon , Alexander Bazarsky , David Gur , Stella Achtenberg
IPC: G06F11/10
Abstract: A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.
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7.发明授权公开(公告)号：US10355712B2
公开(公告)日：2019-07-16
申请号：US15475602
申请日：2017-03-31
Applicant: SanDisk Technologies LLC
Inventor： Rami Rom , Idan Goldenberg , Alexander Bazarsky , Eran Sharon , Ran Zamir , Idan Alrod , Stella Achtenberg
Abstract: A storage device may program data differently for different memory areas of a memory. In some embodiments, the storage device may use different codebooks for different memory areas. In other embodiments, the storage device may modify bit orders differently for different memory areas. What codebook the storage device uses or what bit order modification the storage device performs for a particular memory area may depend on the bad storage locations specific to that memory area. Where different codebooks are used, optimal codebooks may be selected from a library, or codebooks may be modified based on the bad storage locations of the memory areas.
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公开(公告)号：US10075190B2
公开(公告)日：2018-09-11
申请号：US14924627
申请日：2015-10-27
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Stella Achtenberg , Eran Sharon , Ran Zamir
CPC classification number: H03M13/3746 , G06F11/10 , G06F11/1072 , G11C29/52 , H03M13/1108 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/1191 , H03M13/1515 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/45
Abstract: A decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.
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公开(公告)号：US09959168B2
公开(公告)日：2018-05-01
申请号：US15177822
申请日：2016-06-09
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Stella Achtenberg , Eran Sharon , Idan Alrod
CPC classification number: G06F3/0689 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F11/1012 , G06F11/108 , H03M13/1102 , H03M13/1515 , H03M13/2909 , H03M13/2927 , H03M13/3707
Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The controller includes a stripe generator and a stripe decoder. The stripe generator is configured, in response to the number of undecodable codewords exceeding an erasure correction capacity of a stripe correction scheme, to generate trial data for a stripe of the data structure, the trial data including at least one element that corresponds to erased data and at least another element that is associated with an undecodable codeword and that corresponds to valid data of the stripe. The stripe decoder is configured to initiate a stripe decode operation of the trial data.
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公开(公告)号：US09940194B2
公开(公告)日：2018-04-10
申请号：US15177887
申请日：2016-06-09
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Stella Achtenberg , Eran Sharon , Idan Alrod
CPC classification number: G06F3/0689 , G06F3/0619 , G06F3/064 , G06F3/0644 , G06F11/1012 , G06F11/108 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2909 , H03M13/2927 , H03M13/2957 , H03M13/6325
Abstract: A device includes a memory and a controller. The controller is configured to read codewords of a data structure from the memory. The codewords include a number of undecodable codewords that are undecodable at an error correction coding (ECC) decoder according to a first correction scheme. The data structure further includes stripe parity corresponding to portions of the codewords encoded according to a stripe correction scheme. The controller is configured, in response to the number of the undecodable codewords exceeding an erasure correction capacity of the stripe correction scheme, to provide information from a stripe decoding operation to an input of a ECC decoding operation corresponding to an undecodable codeword.
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