公开(公告)号：US20180374866A1

公开(公告)日：2018-12-27

申请号：US15633131

申请日：2017-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka Krishna KANAKAMEDALA ,  Yanli ZHANG ,  Yao-Sheng LEE

IPC: H01L27/11582 ,  H01L29/51 ,  H01L29/423 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/08 ,  H01L21/28 ,  H01L21/311

CPC classification number: H01L27/11582 ,  H01L21/31122 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/0847 ,  H01L29/40117 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A strap level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. An array of memory stack structures is formed through the alternating stack and the strap level sacrificial layer. Each memory film in the memory stack structures includes a metal oxide blocking dielectric. After formation of a source cavity by removal of the strap level sacrificial layer, an atomic layer etch process can be employed to remove portions of the metal oxide blocking dielectrics at the level of the source cavity. Outer sidewalls of semiconductor channels in the memory stack structures are exposed by additional etch processes, and a source strap layer is selectively deposited in the source cavity in contact with the semiconductor channel. If the spacer material layers are sacrificial material layers, all volumes of the sacrificial material layers can be replaced with the electrically conductive layers.

公开(公告)号：US20190148392A1

公开(公告)日：2019-05-16

申请号：US15813625

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yoshihiro KANNO ,  Senaka Krishna KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.

公开(公告)号：US20190148506A1

公开(公告)日：2019-05-16

申请号：US15813579

申请日：2017-11-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Krishna KANAKAMEDALA ,  Yoshihiro KANNO ,  Raghuveer S. MAKALA ,  Yanli ZHANG ,  Jin LIU ,  Murshed CHOWDHURY ,  Yao-Sheng LEE

IPC: H01L29/423 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L29/66 ,  H01L29/49

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.